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Thao P. Le

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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7087497 Low-thermal-budget gapfill process
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US Patent 7091075 Fabrication of an EEPROM cell with SiGe source/drain regions
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US Patent 7091137 Bi-layer approach for a hermetic low dielectric constant layer for barrier applications
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US Patent 7094653 Method for forming STI structures with controlled step height
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US Patent 7095092 Semiconductor device and method of forming the same
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US Patent 7098062 Manufacturing method of pixel structure of thin film transistor liquid crystal display
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US Patent 7098103 Method and structure for non-single-polycrystalline capacitor in an integrated circuit
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US Patent 7101742 Strained channel complementary field-effect transistors and methods of manufacture
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US Patent 7101744 Method for forming self-aligned, dual silicon nitride liner for CMOS devices
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US Patent 7105367 Method of manufacturing array substrate for liquid crystal display device
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US Patent 7105440 Self-forming metal silicide gate for CMOS devices
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US Patent 7105449 Method for cleaning substrate and method for producing semiconductor device
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US Patent 7109045 Method for preparing a ring-formed body, and magnetic memory device and method for manufacturing the same
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US Patent 7109082 Flash memory cell
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US Patent 7109111 Method of annealing metal layers
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US Patent 7109542 Capacitor constructions having a conductive layer
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US Patent 7109560 Micro-electromechanical system and method for production thereof
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US Patent 7109561 Method of manufacturing a semiconductor device and a method for fixing the semiconductor device using substrate jig
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US Patent 7119029 Method of oxidizing a silicon substrate and method of forming an oxide layer using the same
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US Patent 7125730 Power supply, a semiconductor making apparatus and a semiconductor wafer fabricating method using the same
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US Patent 7125812 CVD method and device for forming silicon-containing insulation film
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US Patent 7126164 Wafer-level moat structures
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US Patent 7129162 Dual cap layer in damascene interconnection processes
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US Patent 7129164 Method for forming a multi-layer low-K dual damascene
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US Patent 7132687 Semiconductor device and method of manufacturing the same
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US Patent 7135727 I-shaped and L-shaped contact structures and their fabrication methods
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US Patent 7138656 Liquid crystal display panel and fabricating method thereof
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US Patent 7141859 Porous gas sensors and method of preparation thereof
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US Patent 7144813 Method and apparatus for thermally processing microelectronic workpieces
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US Patent 7144823 Thermal treatment apparatus
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US Patent 7148086 Semiconductor package with controlled solder bump wetting and fabrication method therefor
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US Patent 7151302 Method and apparatus for maintaining topographical uniformity of a semiconductor memory array
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US Patent 7160763 Polycrystalline TFT uniformity through microstructure mis-alignment
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US Patent 7160804 Method of fabricating MOS transistor by millisecond anneal
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US Patent 7160822 Method of forming quantum dots for extended wavelength operation
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US Patent 7161168 Superlattice nanopatterning of wires and complex patterns
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US Patent 7166533 Phase change memory cell defined by a pattern shrink material process
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US Patent 7169661 Process of fabricating high resistance CMOS resistor
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US Patent 7170083 Bipolar transistor with collector having an epitaxial Si:C region
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US Patent 7172937 Method of manufacturing a non-volatile memory cell
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US Patent 7176120 Method of manufacturing semiconductor device
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US Patent 7179749 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region
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US Patent 7179754 Method and apparatus for plasma nitridation of gate dielectrics using amplitude modulated radio-frequency energy
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US Patent 7180128 Non-volatile memory, non-volatile memory array and manufacturing method thereof
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US Patent 7183597 Quantum wire gate device and method of making same
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US Patent 7186578 Thin sheet production method and thin sheet production device
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US Patent 7189603 Thin film transistor substrate and its manufacture
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US Patent 7189610 Semiconductor diode and method therefor
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US Patent 7193238 Display device and a method for manufacturing the same
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US Patent 7193304 Memory card structure
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US Patent 7195929 MRAM including unit cell formed of one transistor and two magnetic tunnel junctions (MTJs) and method for fabricating the same
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US Patent 7195972 Trench capacitor DRAM cell using buried oxide as array top oxide
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US Patent 7196382 Transistor, method for producing an integrated circuit and a method of producing a metal silicide layer
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US Patent 7202523 NROM flash memory devices on ultrathin silicon
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US Patent 7202564 Advanced low dielectric constant organosilicon plasma chemical vapor deposition films
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US Patent 7205233 Method for forming CoWRe alloys by electroless deposition
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US Patent 7205591 Pixel sensor cell having reduced pinning layer barrier potential and method thereof
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US Patent 7205640 Semiconductor device and display comprising same
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US Patent 7208326 Edge protection process for semiconductor device fabrication
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US Patent 7211447 Structure and method to fabricate high performance MTJ devices for MRAM applications
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US Patent 7211904 Pad structure for bonding pad and probe pad and manufacturing method thereof
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US Patent 7217615 Capacitor fabrication methods including forming a conductive layer
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US Patent 7217646 Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement
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US Patent 7226815 Method for manufacturing semiconductor device
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US Patent 7226844 Method of manufacturing a bipolar transistor with a single-crystal base contact
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US Patent 7229860 Method for manufacturing a thin film transistor using poly silicon
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US Patent 7229868 Organic field-effect transistor, method for structuring an OFET and integrated circuit
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US Patent 7229881 Dynamic random access memory of semiconductor device and method for manufacturing the same
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US Patent 7229897 Method for producing a stacked structure
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US Patent 7230279 Memory card
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US Patent 7230342 Registration mark within an overlap of dopant regions
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US Patent 7232719 Memories having a charge storage node at least partially located in a trench in a semiconductor substrate and electrically coupled to a source/drain region formed in the substrate
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US Patent 7232741 Wafer dividing method
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US Patent 7232770 High temperature and chemical resistant process for wafer thinning and backside processing
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US Patent 7235434 Thin film transistor with multiple gates using metal induced lateral crystallization and method of fabricating the same
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US Patent 7235435 Method for fabricating thin film transistor with multiple gates using metal induced lateral crystallization
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US Patent 7235445 Methods of forming device with recessed gate electrodes
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US Patent 7235491 Method of manufacturing spacer
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US Patent 7238554 Simultaneous planar and non-planar thin-film transistor processes
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US Patent 7238562 Method for fabricating CMOS image sensor
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US Patent 7238598 Formation of a semiconductor substrate that may be dismantled and obtaining a semiconductor element
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US Patent 7238611 Salicide process
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US Patent 7241678 Integrated die bumping process
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US Patent 7242058 Lateral semiconductor device using trench structure and method of manufacturing the same
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US Patent 7247528 Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques
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US Patent 7247536 Vertical DRAM device with self-aligned upper trench shaping
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US Patent 7253011 Fabrication method of semiconductor integrated circuit device
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US Patent 7253036 Method of forming gate insulation film using plasma method of fabricating poly-silicon thin film transistor using the same
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US Patent 7253072 Implant optimization scheme
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US Patent 7253106 Manufacturable CoWP metal cap process for copper interconnects
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US Patent 7256066 Flip chip packaging process
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US Patent 7256090 Method for fabricating semiconductor device
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US Patent 7256441 Partially recessed DRAM cell structure
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US Patent 7256444 Local SONOS-type nonvolatile memory device and method of manufacturing the same
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US Patent 7259024 Method of treating a substrate in manufacturing a magnetoresistive memory cell
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US Patent 7259044 Lead frame, method of manufacturing the same, and method of manufacturing a semiconductor device using the same
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US Patent 7262454 Thin film transistor substrate and fabricating method thereof
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US Patent 7265017 Method for manufacturing partial SOI substrates
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US Patent 7265044 Method for forming bump on electrode pad with use of double-layered film
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US Patent 7265374 Light emitting semiconductor device
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US Patent 7265409 Non-volatile semiconductor memory
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US Patent 7268421 Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
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US Patent 7268425 Thermally enhanced electronic flip-chip packaging with external-connector-side die and method
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US Patent 7271010 Nonvolatile magnetic memory device and manufacturing method thereof
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US Patent 7271015 Manufacturing method of semiconductor integrated circuit device and probe card
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US Patent 7271044 CMOS (complementary metal oxide semiconductor) technology
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US Patent 7271495 Chip bond layout for chip carrier for flip chip applications
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US Patent 7273763 Method of producing a micro-electromechanical element
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US Patent 7276413 NROM flash memory devices on ultrathin silicon
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US Patent 7276421 Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby
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US Patent 7276424 Fabrication of aligned nanowire lattices
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US Patent 7276436 Manufacturing method for electronic component module and electromagnetically readable data carrier
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US Patent 7276762 NROM flash memory devices on ultrathin silicon
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US Patent 7276790 Methods of forming a multi-chip module having discrete spacers
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US Patent 7279381 Method for fabricating cell transistor of flash memory
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US Patent 7279395 Suppression of dark current in a photosensor for imaging
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US Patent 7282401 Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
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US Patent 7282755 Stress assisted current driven switching for magnetic memory applications
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US Patent 7285472 Low tolerance polysilicon resistor for low temperature silicide processing
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US Patent 7285491 Salicide process
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US Patent 7288455 Method of forming non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors
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US Patent 7288478 Method for performing chemical shrink process over BARC (bottom anti-reflective coating)
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US Patent 7291520 Piezoelectric element and liquid jet head using the piezoelectric element
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US Patent 7291559 Etching method, gate etching method, and method of manufacturing semiconductor devices
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US Patent 7291877 Integrated circuit arrangement with capacitor
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US Patent 7294537 Method of fabricating thin film transistor with multiple gates using super grain silicon crystallization
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US Patent 7297625 Group III-V crystal and manufacturing method thereof
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US Patent 7300876 Method for cleaning slurry particles from a surface polished by chemical mechanical polishing
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US Patent 7301190 Structures and methods to enhance copper metallization
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US Patent 7301202 Semiconductor device and method of manufacturing the same
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US Patent 7309628 Method of forming a semiconductor device
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US Patent 7312110 Methods of fabricating semiconductor devices having thin film transistors
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US Patent 7312147 Method of forming barrier metal in semiconductor device
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US Patent 7312475 Optical element and its manufacturing method
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US Patent 7312476 Optical element and its manufacturing method
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US Patent 7314787 Method of manufacturing a semiconductor device
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US Patent 7314791 Bipolar transistor for an integrated circuit having variable value emitter ballast resistors
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US Patent 7314822 Method of fabricating stacked local interconnect structure
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US Patent 7314825 Method for forming contact plug of semiconductor device
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US Patent 7314826 Semiconductor device and method of fabricating the same
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US Patent 7319260 Hinged bonding of micromechanical devices
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US Patent 7321143 Ion-sensitive field effect transistor and method for producing an ion-sensitive field effect transistor
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US Patent 7323368 Method for manufacturing semiconductor device and heat treatment method
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US Patent 7323734 Phase changeable memory cells
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US Patent 7329579 Phase changeable memory cells and methods of fabricating the same
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US Patent 7329600 Low dielectric semiconductor device and process for fabricating the same
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US Patent 7332380 Pattern design method and program of a semiconductor device including dummy patterns
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US Patent 7332819 Stacked die in die BGA package
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US Patent 7335607 Method of forming a gate dielectric layer
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US Patent 7335941 Uniform channel programmable erasable flash EEPROM
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US Patent 7335982 Chip package structure and chip packaging process
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US Patent 7335986 Wafer level chip scale package
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US Patent 7338847 Methods of manufacturing a stressed MOS transistor structure
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US Patent 7338857 Increasing adherence of dielectrics to phase change materials
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US Patent 7338868 Method for forming gate oxide layer in semiconductor device
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US Patent 7341940 Method for forming metal wirings of semiconductor device
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US Patent 7342280 Non-volatile memory and method of fabricating the same
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US Patent 7344949 Non-volatile memory device and method of fabricating the same
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US Patent 7344969 Stacked die in die BGA package
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US Patent 7345332 Semiconductor constructions
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US Patent 7345370 Wiring patterns formed by selective metal plating
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US Patent 7348199 Wafer dividing method
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US Patent 7348238 Bottom electrode for memory device and method of forming the same
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US Patent 7351645 Pressure sensitive adhesive sheet for use in semiconductor working and method for producing semiconductor chip
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US Patent 7351657 Method and apparatus for applying external coating to grid array packages for increased reliability and performance
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US Patent 7352022 Capacitor having a dielectric layer that reduces leakage current and a method of manufacturing the same
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US Patent 7352030 Semiconductor devices with buried isolation regions
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US Patent 7352055 Semiconductor package with controlled solder bump wetting
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US Patent 7354807 Method of fabricating liquid crystal display panel
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US Patent 7354857 Method of making iron silicide and method of making photoelectric transducer
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US Patent 7358117 Stacked die in die BGA package
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US Patent 7358125 Method of forming thin film transistor substrate
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US Patent 7358145 Method of fabricating shallow trench isolation structure
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US Patent 7358562 NROM flash memory devices on ultrathin silicon
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US Patent 7358584 Imaging sensor
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US Patent 7361945 Semiconductor device
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US Patent 7364978 Method of fabricating semiconductor device
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US Patent 7368389 Methods of forming electrically conductive plugs
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US Patent 7368756 Trench cut light emitting diodes and methods of fabricating same
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US Patent 7371604 Method of forming a contact structure
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US Patent 7371626 Method for maintaining topographical uniformity of a semiconductor memory array
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US Patent 7371628 Method for fabricating semiconductor device
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US Patent 7372094 Semiconductor constructions
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US Patent 7378303 Method of fabricating thin film transistor
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US Patent 7378316 Method for fabricating semiconductor vertical NROM memory cells
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US Patent 7378338 Method of forming an interconnect structure diffusion barrier with high nitrogen content
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US Patent 7378737 Structures and methods to enhance copper metallization
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US Patent 7381611 Multilayered phase change memory
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US Patent 7381616 Method of making three dimensional, 2R memory having a 4F2 cell size RRAM
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US Patent 7381990 Thin film transistor with multiple gates fabricated using super grain silicon crystallization
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US Patent 7384855 Resistor integration structure and technique for noise elimination
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US Patent 7387930 Method of fabricating a bottle trench and a bottle trench capacitor
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US Patent 7387932 Method for manufacturing a multiple-gate charge trapping non-volatile memory
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US Patent 7393700 Low temperature methods of etching semiconductor substrates
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US Patent 7393739 Demultiplexers using transistors for accessing memory cell arrays
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US Patent 7393745 Method for fabricating self-aligned double layered silicon-metal nanocrystal memory element
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US Patent 7393787 Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment
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US Patent 7396730 Integrated circuit devices including an L-shaped depletion barrier layer adjacent opposite sides of a gate pattern and methods of forming the same
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US Patent 7396731 Method for preparing a non-self-aligned heterojunction bipolar transistor with a small emitter-to-base spacing
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US Patent 7399655 Damascene conductive line for contacting an underlying memory element
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US Patent 7399695 Integrated die bumping process
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US Patent 7402461 Method of connecting base materials
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US Patent 7402478 Method of fabricating dual gate electrode of CMOS semiconductor device
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US Patent 7402510 Etchant and method for forming bumps
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US Patent 7402853 BST integration using thin buffer layer grown directly onto SiO
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US Patent 7402877 Micromachine and method of manufacturing the micromachine
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US Patent 7405429 Pixel structure
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US Patent 7407885 Methods of forming electrically conductive plugs
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US Patent 7410866 Method for forming storage node of capacitor in semiconductor device
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US Patent 7416914 Method of fabricating CMOS image sensor
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US Patent 7422933 Method of manufacturing semiconductor device
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US Patent 7425746 Semiconductor storage device and semiconductor integrated circuit
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US Patent 7427562 Method for fabricating closed vias in a printed circuit board
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US Patent 7432187 Method for improving current distribution of a transparent electrode
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US Patent 7432572 Method for stripping sacrificial layer in MEMS assembly
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US Patent 7435642 Method of evaluating the uniformity of the thickness of the polysilicon gate layer
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US Patent 7435646 Method for forming floating gates within NVM process
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US Patent 7439082 Conductive memory stack with non-uniform width
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US Patent 7439120 Method for fabricating stress enhanced MOS circuits
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US Patent 7442595 Bipolar transistor with collector having an epitaxial Si:C region
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US Patent 7442967 Strained channel complementary field-effect transistors
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US Patent 7445977 Method of creating defect free high Ge content (> 25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
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US Patent 7445992 Method for fabricating cell structure of non-volatile memory device
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US Patent 7446025 Method of forming vertical FET with nanowire channels and a silicided bottom contact
‌
US Patent 7446355 Electrical device and method for fabricating the same
‌
US Patent 7449388 Method for forming multiple doping level bipolar junctions transistors
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US Patent 7452812 Method to create super secondary grain growth in narrow trenches
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US Patent 7456472 Semiconductor device and manufacturing method thereof
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US Patent 7459360 Method of forming pixel sensor cell having reduced pinning layer barrier potential
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US Patent 7459739 Double density MRAM with planar processing
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US Patent 7459748 Semiconductor memory device
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US Patent 7459756 Method for forming a device having multiple silicide types
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US Patent 7459792 Via layout with via groups placed in interlocked arrangement
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US Patent 7462528 CMOS (Complementary metal oxide semiconductor) technology with leakage current mitigation
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US Patent 7468304 Method of fabricating oxide semiconductor device
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US Patent 7470142 Wafer bonding method
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US Patent 7470570 Process for fabrication of FinFETs
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US Patent 7470579 Method of manufacturing a thin film transistor
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US Patent 7470608 Semiconductor light emitting device and fabrication method thereof
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US Patent 7470615 Semiconductor structure with self-aligned device contacts
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US Patent 7470922 Increasing adherence of dielectrics to phase change materials
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US Patent 7473565 Semiconductor device and method of manufacturing the same
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US Patent 7473594 Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
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US Patent 7482204 Chip packaging process
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US Patent 7482207 Electronic devices
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US Patent 7485477 Thin plate manufacturing method and thin plate manufacturing apparatus
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US Patent 7485484 Group III-V crystal
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US Patent 7485517 Fabricating method of semiconductor device
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US Patent 7485529 Method of fabricating non-volatile memory
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US Patent 7485530 Method for manufacturing a multiple-gate charge trapping non-volatile memory
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US Patent 7485556 Forming metal silicide on silicon-containing features of a substrate
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US Patent 7485577 Method of forming metal line stacking structure in semiconductor device
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US Patent 7491596 Fabrication method of CMOS image sensor integrated with 1-T SRAM
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US Patent 7492039 Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads
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US Patent 7494919 Method for post lithographic critical dimension shrinking using thermal reflow process
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US Patent 7495307 Columnar electric device
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US Patent 7498194 Semiconductor arrangement
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US Patent 7498246 Method of manufacturing a semiconductor device having a stepped gate structure
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US Patent 7498259 Through electrode and method for forming the same
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US Patent 7504686 Self-aligned non-volatile memory cell
‌
US Patent 7510898 Method of manufacturing image display device and method of dividing device
‌
US Patent 7514308 CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers
‌
US Patent 7514373 Method and apparatus for plasma nitridation of gate dielectrics using amplitude modulated radio-frequency energy
‌
US Patent 7514725 Nanophotovoltaic devices
‌
US Patent 7521808 Wiring paterns formed by selective metal plating
‌
US Patent 7531402 Method of manufacturing semiconductor device with offset sidewall structure
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US Patent 7531441 Method of manufacturing semiconductor device
‌
US Patent 7534630 Method of improving power distribution in wirebond semiconductor packages
‌
US Patent 7534720 Methods of fabricating semiconductor device having slope at lower sides of interconnection hole with etch-stop layer
‌
US Patent 7535103 Structures and methods to enhance copper metallization
‌
US Patent 7537992 Method for manufacturing flash memory device
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US Patent 7544566 Method for manufacturing a non-volatile electrically alterable memory cell that stores multiple data
‌
US Patent 7544601 Semiconductor device and a method for manufacturing the same
‌
US Patent 7550302 Method of manufacturing semiconductor device
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US Patent 7554121 Organic semiconductor device
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US Patent 7554171 Semiconductor constructions
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US Patent 7560338 Manufacturing method of non-volatile memory
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US Patent 7563633 Microelectromechanical systems encapsulation process
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US Patent 7563721 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region
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US Patent 7564064 Semiconductor light emitting device, an integrated semiconductor light emitting apparatus, an image display apparatus, and an illuminating apparatus having a semiconductor layer with conical crystal portion
‌
US Patent 7564117 Bipolar transistor having variable value emitter ballast resistors
‌
US Patent 7566926 Nonvolatile semiconductor memory
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US Patent 7569933 Housing for accommodating microwave devices having an insulating cup member
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US Patent 7573115 Structure and method for enhancing resistance to fracture of bonding pads
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US Patent 7573122 Method for producing a semiconductor component having a metallic control electrode, and semiconductor component
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US Patent 7576376 Suppression of dark current in a photosensor for imaging
‌
US Patent 7579673 Semiconductor device having electrical fuse
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US Patent 7582514 Microelectromechanical systems encapsulation process with anti-stiction coating
‌
US Patent 7582917 Monolithically integrated light-activated thyristor and method
‌
US Patent 7588945 Multi-state thermally assisted storage
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US Patent 7589348 Thermal tunneling gap diode with integrated spacers and vacuum seal
‌
US Patent 7589395 Multiple-dice packages using elements between dice to control application of underfill material to reduce void formation
‌
US Patent 7589422 Micro-element package having a dual-thickness substrate and manufacturing method thereof
‌
US Patent 7592203 Method of manufacturing an electronic protection device
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US Patent 7592205 Over-passivation process of forming polymer layer over IC chip
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US Patent 7592260 Method of manufacturing a semiconductor device
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US Patent 7592672 Grounding structure of semiconductor device including a conductive paste
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US Patent 7595219 IC chip mounting method for mounting two or more IC chips by sequentially transferring the IC chips sucked onto a first roller to a second roller and mounting the IC chips transferred to the second roller on a traveling base
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US Patent 7605045 Field effect transistors and methods for fabricating the same
‌
US Patent 7608492 Method for manufacturing semiconductor device and heat treatment method
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US Patent 7608505 Method of manufacturing non-volatile memory device
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US Patent 7615442 Method for fabricating trench metal-oxide-semiconductor field effect transistor
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US Patent 7615483 Printed metal mask for UV, e-beam, ion-beam and X-ray patterning
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US Patent 7615865 Standoff height improvement for bumping technology using solder resist
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US Patent 7619262 Method and device for electrostatic discharge protection
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US Patent 7629224 VLSI fabrication processes for introducing pores into dielectric materials
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US Patent 7632738 Wafer bonding method
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US Patent 7642161 Method of fabricating recess gate in semiconductor device
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US Patent 7642162 Semiconductor device and method of manufacturing the same
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US Patent 7645633 Method and apparatus for applying external coating to grid array packages for increased reliability and performance
‌
US Patent 7646063 Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions
‌
US Patent 7648863 Semiconductor device and manufacturing method thereof
‌
US Patent 7651911 Memory transistor and methods
‌
US Patent 7652380 Semiconductor device and method of producing the same
‌
US Patent 7659156 Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer
‌
US Patent 7663217 Semiconductor device package
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US Patent 7667233 Display device, flat lamp and method of fabricating the display device and flat lamp
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US Patent 7670901 Method of fabricating a bottle trench and a bottle trench capacitor
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US Patent 7675081 Surface mount optoelectronic component with lens having protruding structure
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US Patent 7678632 MuGFET with increased thermal mass
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US Patent 7678633 Method for forming substrates for MOS transistor components and its products
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US Patent 7678701 Flexible substrate with electronic devices formed thereon
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US Patent 7679099 Low thermal resistance high power LED
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US Patent 7682965 Method for manufacturing semiconductor device
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US Patent 7683463 Etched leadframe structure including recesses
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US Patent 7683481 Bottom electrode for memory device and method of forming the same
‌
US Patent 7683490 Semiconductor integrated circuit and semiconductor device having multilayer interconnection
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US Patent 7687394 Method for forming inter-layer dielectric of low dielectric constant and method for forming copper wiring using the same
‌
US Patent 7687844 Semiconductor constructions
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US Patent 7691695 Semiconductor device having strip-shaped channel and method for manufacturing such a device
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US Patent 7692307 Compliant structure for an electronic device, method of manufacturing same, and system containing same
‌
US Patent 7704769 Optical device manufacturing method
‌
US Patent 7704817 Method for manufacturing semiconductor device
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US Patent 7709827 Vertically integrated field-effect transistor having a nanostructure therein
‌
US Patent 7713811 Multiple doping level bipolar junctions transistors and method for forming
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US Patent 7718534 Planarization of a heteroepitaxial layer
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US Patent 7723171 Semiconductor device and method of fabricating the same
‌
US Patent 7723228 Reduction of hillocks prior to dielectric barrier deposition in Cu damascene
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US Patent 7727801 Apparatus for improved power distribution in wirebond semiconductor packages
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US Patent 7728352 Damascene conductive line for contacting an underlying memory element
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US Patent 7732320 Apparatus and method for semiconductor wafer bumping via injection molded solder
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US Patent 7737022 Contact formation
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US Patent 7745283 Method of fabricating memory transistor
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US Patent 7745849 Enhancement mode III-nitride semiconductor device with reduced electric field between the gate and the drain
‌
US Patent 7745935 Method to create super secondary grain growth in narrow trenches
‌
US Patent 7749804 Organic semiconductor device and method for manufacturing the same
‌
US Patent 7749905 Vertical Fet with nanowire channels and a silicided bottom contact
‌
US Patent 7750483 Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
‌
US Patent 7759175 Fabrication method of a mixed substrate and use of the substrate for producing circuits
‌
US Patent 7759211 Method of fabricating semiconductor device
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US Patent 7763493 Integrated circuit package system with top and bottom terminals
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US Patent 7763527 Semiconductor element, semiconductor device, and method for fabrication thereof
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US Patent 7763912 Columnar electric device and production method thereof
‌
US Patent 7768058 NROM flash memory devices on ultrathin silicon
‌
US Patent 7772102 Nonvolatile semiconductor memory and fabrication method for the same
‌
US Patent 7772612 Nanophotovoltaic devices
‌
US Patent 7776628 Method and system for tone inverting of residual layer tolerant imprint lithography
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US Patent 7776639 Suppression of dark current in a photosensor for imaging
‌
US Patent 7777298 Semiconductor device and method of manufacturing the same
‌
US Patent 7790572 Method for manufacturing semiconductor substrate
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US Patent 7795058 Method for manufacturing optical element
‌
US Patent 7795142 Method for fabricating a semiconductor device
‌
US Patent 7799675 Bonded semiconductor structure and method of fabricating the same
‌
US Patent 7800199 Semiconductor circuit
‌
US Patent 7803710 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region
‌
US Patent 7807559 Bonding pad for preventing pad peeling and method for fabricating the same
‌
US Patent 7808071 Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof
‌
US Patent 7812397 Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof
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US Patent 7820546 Method for manufacturing semiconductor device preventing loss of junction region
‌
US Patent 7821048 Double density MRAM with planar processing
‌
US Patent 7824967 Monolithically integrated light-activated thyristor and method
‌
US Patent 7824979 Semiconductor device with channel of FIN structure and method for manufacturing the same
‌
US Patent 7824992 Method of fabricating non-volatile memory device
‌
US Patent 7829926 Demultiplexers using transistors for accessing memory cell arrays
‌
US Patent 7830016 Seed layer for reduced resistance tungsten film
‌
US Patent 7833812 Process for forming optical device having electron injection layer comprising barium
‌
US Patent 7833875 Semiconductor device and method of fabricating the same
‌
US Patent 7838325 Method to optimize substrate thickness for image sensor device
‌
US Patent 7838369 Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications
‌
US Patent 7838428 Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species
‌
US Patent 7838865 Method for aligning elongated nanostructures
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US Patent 7838932 Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
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US Patent 7842598 Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument
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US Patent 7846821 Multi-angle rotation for ion implantation of trenches in superjunction devices
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US Patent 7851319 Method for preparing a non-self-aligned heterojunction bipolar transistor with a small emitter-to-base spacing
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US Patent 7855101 Layer transfer process and functionally enhanced integrated circuits produced thereby
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US Patent 7858457 Methods of forming integrated circuit devices including a depletion barrier layer at source/drain regions
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US Patent 7858503 Ion implanted substrate having capping layer and method
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US Patent 7859095 Method of manufacturing semiconductor device
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US Patent 7863078 Method for making an anti-reflection film of a solar cell
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US Patent 7863700 Magnetoresistive sensor with tunnel barrier and method
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US Patent 7863748 Semiconductor circuit and method of fabricating the same
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US Patent 7867822 Semiconductor memory device
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US Patent 7867887 Structure and method for enhancing resistance to fracture of bonding pads
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US Patent 7872260 Fabrication method of pixel structure and thin film transistor
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US Patent 7875495 Standoff height improvement for bumping technology using solder resist
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US Patent 7883962 Trench DRAM cell with vertical device and buried word lines
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US Patent 7884396 Method and structure for self-aligned device contacts
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US Patent 7888192 Process for forming integrated circuits with both split gate and common gate FinFET transistors
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US Patent 7888245 Plasma doping method and method for fabricating semiconductor device using the same
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US Patent 7888704 Semiconductor device for electrostatic discharge protection
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US Patent 7888764 Three-dimensional integrated circuit structure
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US Patent 7892984 Reduction of defects formed on the surface of a silicon oxynitride film
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US Patent 7898046 Microelectromechanical systems encapsulation process
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US Patent 7902603 Semiconductor device and method of manufacturing the same
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US Patent 7902616 Integrated circuit having a magnetic tunnel junction device and method
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US Patent 7902631 Contact plug structure
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US Patent 7906775 Superlattice nanopatterning of wires and complex patterns
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US Patent 7906822 Packaged device and method of manufacturing the same
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US Patent 7910458 Method and structure using selected implant angles using a linear accelerator process for manufacture of free standing films of materials
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US Patent 7910492 Nanowhiskers with PN junctions, doped nanowhiskers, and methods for preparing them
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US Patent 7911002 Semiconductor device with selectively modulated gate work function
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US Patent 7915092 Nonvolatile memory with a unified cell structure
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US Patent 7915669 NROM flash memory devices on ultrathin silicon
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US Patent 7919412 Over-passivation process of forming polymer layer over IC chip
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US Patent 7928453 Semiconductor light emitting device
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US Patent 7928495 Semiconductor device and method of fabricating the same
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US Patent 7932149 Method of manufacturing a semiconductor device
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US Patent 7932548 Systems and methods for fabricating self-aligned memory cell
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US Patent 7935604 Method of making small geometry features
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US Patent 7939444 Manufacturing methods of thin film solar cell and thin film solar cell module
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US Patent 7943465 Method for manufacturing a semiconductor component
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US Patent 7943527 Surface preparation for thin film growth by enhanced nucleation
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US Patent 7943528 Substrate processing apparatus and semiconductor devices manufacturing method
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US Patent 7943999 Stress enhanced MOS circuits
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US Patent 7947599 Laser annealing for 3-D chip integration
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US Patent 7951696 Methods for simultaneously forming N-type and P-type doped regions using non-contact printing processes
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US Patent 7952182 Semiconductor device with package to package connection
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US Patent 7956406 Nonvolatile semiconductor memory device
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US Patent 7960225 Method of controlling film thinning of semiconductor wafer for solid-state image sensing device
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US Patent 7960282 Method of manufacture an integrated circuit system with through silicon via
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US Patent 7964507 Flexible substrate with electronic devices formed thereon
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US Patent 7972876 Zinc-oxide-based semiconductor light-emitting device and method of fabricating the same
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US Patent 7972908 Method of switching off a monolithically integrated optically controlled thyristor
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US Patent 7972976 VLSI fabrication processes for introducing pores into dielectric materials
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US Patent 7977123 Arrangements and methods for improving bevel etch repeatability among substrates
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US Patent 7977231 Die bonder incorporating dual-head dispenser
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US Patent 7977695 Semiconductor light emitting device and method for manufacturing the same
‌
US Patent 7977719 Magneto-resistance effect element and magnetic memory
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US Patent 7985644 Methods for forming fully segmented salicide ballasting (FSSB) in the source and/or drain region
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US Patent 7989254 Method for fabricating color filter using surface plasmon and method for fabricating liquid crystal display device
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US Patent 7993965 Process for producing semiconductive porcelain composition/electrode assembly
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US Patent 7998782 Fabrication of image sensor with improved signal to noise ratio
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US Patent 7998836 Method for fabricating gallium nitride based semiconductor electronic device
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US Patent 7998838 Method and apparatus for scribing a line in a thin film using a series of laser pulses
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US Patent 7998854 Wafer level integration module with interconnects
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US Patent 8000479 Wireless speaker adapter
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US Patent 8008119 Surface mount optoelectronic component with lens having protruding structure
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US Patent 8008670 Light emitting device
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US Patent 8008692 Semiconductor memory structure with stress regions
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US Patent 8012856 Method of producing semiconductor components
Edits on 13 Dec, 2021
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US Patent 8012856 Method of producing semiconductor components
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edited on 8 Dec, 2021
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US Patent 8008692 Semiconductor memory structure with stress regions
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edited on 8 Dec, 2021
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US Patent 8008670 Light emitting device
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edited on 8 Dec, 2021
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Infobox
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US Patent 8008119 Surface mount optoelectronic component with lens having protruding structure
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edited on 8 Dec, 2021
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US Patent 8000479 Wireless speaker adapter
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edited on 8 Dec, 2021
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US Patent 7998854 Wafer level integration module with interconnects
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edited on 8 Dec, 2021
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US Patent 7998838 Method and apparatus for scribing a line in a thin film using a series of laser pulses
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edited on 8 Dec, 2021
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US Patent 7998782 Fabrication of image sensor with improved signal to noise ratio
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edited on 8 Dec, 2021
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US Patent 7998836 Method for fabricating gallium nitride based semiconductor electronic device
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edited on 8 Dec, 2021
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US Patent 7993965 Process for producing semiconductive porcelain composition/electrode assembly
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edited on 8 Dec, 2021
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edited on 8 Dec, 2021
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edited on 8 Dec, 2021
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US Patent 7977719 Magneto-resistance effect element and magnetic memory
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edited on 8 Dec, 2021
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US Patent 7977695 Semiconductor light emitting device and method for manufacturing the same
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edited on 8 Dec, 2021
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US Patent 7977231 Die bonder incorporating dual-head dispenser
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edited on 8 Dec, 2021
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US Patent 7977123 Arrangements and methods for improving bevel etch repeatability among substrates
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edited on 8 Dec, 2021
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US Patent 7972976 VLSI fabrication processes for introducing pores into dielectric materials
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edited on 8 Dec, 2021
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US Patent 7972908 Method of switching off a monolithically integrated optically controlled thyristor
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US Patent 7972876 Zinc-oxide-based semiconductor light-emitting device and method of fabricating the same

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