Patent attributes
A non-volatile semiconductor memory having a memory transistor including a stacked-layer film formed between a semiconductor substrate and a gate electrode and having a charge storage ability, a first conductivity type region of the semiconductor substrate in which a channel is formed under the control of the gate electrode via the stacked-layer film, and two second conductivity type regions formed at the semiconductor substrate sandwiching the first conductivity type region therebetween, the memory transistor having a channel length L which is between channel lengths L1 and L2. with the channel length L1 being estimated as the boundary of occurrence of a short channel effect at the time of a write operation and the channel length L2 the time of a read operation, with the channel length L1 being different from the channel length L2.
