US Patent 7470615 Semiconductor structure with self-aligned device contacts

Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact being enlarged to reduce resistance without impacting device yield. The semiconductor structure includes a substrate; at least two gate electrodes on the substrate; sidewall spacers adjacent to each of the gate electrodes; a silicide region on the substrate between the gate electrodes; and a contact on the silicide region, wherein the contact includes a self-aligned lower portion on the silicide region, which extends between the sidewall spacers and follows contours of the sidewall spacers, and an upper portion, and wherein the self-aligned lower portion includes a bottom surface adjacent to the silicide region and a top surface adjacent to the upper portion, with the upper portion being narrower than the top surface. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility.