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Thanhha Pham

based in Vietnam

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Edits on 26 Sep, 2022
"Infobox creation from: https://twitter.com/rytamee"
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edited on 26 Sep, 2022
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Location
Vietnam
Vietnam
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Roman Beliaev
edited on 26 Sep, 2022
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Twitter URL
https://twitter.com/rytamee
Edits on 14 Dec, 2021
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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7087948 Forming electronic structures having dual dielectric thicknesses and the structure so formed
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US Patent 7091079 Method of forming devices having three different operation voltages
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US Patent 7094668 Annealing process and device of semiconductor wafer
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US Patent 7094681 Semiconductor device fabrication method
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US Patent 7098047 Wafer reuse techniques
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US Patent 7098049 Shallow trench isolation void detecting method and structure for the same
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US Patent 7098127 Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment
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US Patent 7098129 Interlayer insulation film used for multilayer interconnect of semiconductor integrated circuit and method of manufacturing the same
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US Patent 7101735 Manufacturing method of semiconductor device
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US Patent 7101784 Method to generate porous organic dielectric
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US Patent 7105439 Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology
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US Patent 7112473 Double side stack packaging method
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US Patent 7118963 Semiconductor memory integrated circuit and its manufacturing method
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US Patent 7118976 Methods of manufacturing MOSFETs in semiconductor devices
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US Patent 7122824 Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof
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US Patent 7125778 Method for fabricating a self-aligning mask
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US Patent 7129104 Wavelength-insensitive radiation coupling for multi-quantum well sensor based on intersubband absorption
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US Patent 7135763 Technique for attaching die to leads
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US Patent 7141866 Apparatus for imprinting lithography and fabrication thereof
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US Patent 7176079 Method of fabricating a semiconductor device with a wet oxidation with steam process
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US Patent 7183199 Method of reducing the pattern effect in the CMP process
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US Patent 7195975 Method of forming bit line contact via
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US Patent 7196001 Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
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US Patent 7199009 Method for fabricating power mosfet
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US Patent 7199060 Method for patterning dielectric layers on semiconductor substrates
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US Patent 7199473 Integrated low-k hard mask
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US Patent 7378343 Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content
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US Patent 7378350 Formation of low resistance via contacts in interconnect structures
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US Patent 7384830 Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
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US Patent 7394155 Top and sidewall bridged interconnect structure and method
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US Patent 7396701 Electronic device and manufacturing method of the same
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US Patent 7396724 Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals
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US Patent 7396759 Protection of Cu damascene interconnects by formation of a self-aligned buffer layer
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US Patent 7399673 Method of forming a charge-trapping memory device
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US Patent 7410895 Methods for forming interconnect structures
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US Patent 7411272 Semiconductor device and method of forming a semiconductor device
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US Patent 7413989 Method of manufacturing semiconductor device
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US Patent 7416951 Thin film resistors integrated at two different metal interconnect levels of single die
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US Patent 7423346 Post passivation interconnection process and structures
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US Patent 7427773 Layer transfer of low defect SiGe using an etch-back process
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US Patent 7429511 Method of forming a tunneling insulating layer in nonvolatile memory device
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US Patent 7432536 LED with self aligned bond pad
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US Patent 7435640 Method of fabricating gate structure
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US Patent 7439156 Method for manufacturing semiconductor device
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US Patent 7445985 DRAM memory and method for fabricating a DRAM memory cell
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US Patent 7449368 Technique for attaching die to leads
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US Patent 7453103 Semiconductor constructions
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US Patent 7465598 Solid-state imaging device and method for fabricating same
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US Patent 7466026 Passivation layer assembly on a substrate and display substrate having the same
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US Patent 7470567 Semiconductor device and method of manufacturing the same
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US Patent 7470583 Method of improved high K dielectric-polysilicon interface for CMOS devices
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US Patent 7473614 Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer
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US Patent 7482252 Method for reducing floating body effects in SOI semiconductor device without degrading mobility
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US Patent 7485485 Method and apparatus for making a MEMS scanner
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US Patent 7485519 After gate fabrication of field effect transistor having tensile and compressive regions
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US Patent 7488669 Method to make markers for double gate SOI processing
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US Patent 7489031 High power radiation emitter device and heat dissipating package for electronic components
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US Patent 7492008 Control of buried oxide in SIMOX
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US Patent 7501343 Formation of boride barrier layers using chemisorption techniques
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US Patent 7501344 Formation of boride barrier layers using chemisorption techniques
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US Patent 7504303 Trench-gate field effect transistors and methods of forming the same
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US Patent 7507652 Methods of forming a composite dielectric structure and methods of manufacturing a semiconductor device including a composite dielectric structure
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US Patent 7510909 Fabricating method of wafer protection layers
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US Patent 7517749 Method for forming an array with polysilicon local interconnects
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US Patent 7517791 Method for manufacturing semiconductor device
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US Patent 7518244 Reducing line to line capacitance using oriented dielectric films
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US Patent 7521263 Method of forming an insulating film, method of manufacturing a semiconductor device, and semiconductor device
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US Patent 7521357 Methods of forming metal wiring in semiconductor devices using etch stop layers
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US Patent 7528021 Thin film transistor array panel and method of manufacturing the same
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US Patent 7528067 MOSFET structure with multiple self-aligned silicide contacts
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US Patent 7528075 Self-masking defect removing method
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US Patent 7528436 Scalable electrically eraseable and programmable memory
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US Patent 7534641 Method for manufacturing a micro-electro-mechanical device
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US Patent 7534721 Semiconductor device manufacturing device
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US Patent 7535100 Wafer bonding of thinned electronic materials and circuits to high performance substrates
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US Patent 7535106 Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate
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US Patent 7537970 Bi-directional transistor with by-pass path and method therefor
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US Patent 7544623 Method for fabricating a contact hole
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US Patent 7547616 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics
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US Patent 7550385 Amine-free deposition of metal-nitride films
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US Patent 7553746 Method for manufacturing electrodes on a semiconducting material of type II-VI or on a compound of this material
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US Patent 7553750 Method for fabricating electrical conductive structure of circuit board
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US Patent 7553760 Sub-lithographic nano interconnect structures, and method for forming same
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US Patent 7554200 Semiconductor devices including porous insulators
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US Patent 7557037 Method of manufacturing semiconductor chip
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US Patent 7560780 Active region spacer for semiconductor devices and method to form the same
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US Patent 7564084 Dual-gate dynamic random access memory device having vertical channel transistors and method of fabricating the same
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US Patent 7566608 Methods of forming thin layers including zirconium hafnium oxide and methods of forming gate structures, capacitors, and flash memory devices using the same
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US Patent 7566631 Low temperature fusion bonding with high surface energy using a wet chemical treatment
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US Patent 7566659 Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same
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US Patent 7569447 Method of forming transistor structure having stressed regions of opposite types
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US Patent 7569468 Method for forming a floating gate memory with polysilicon local interconnects
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US Patent 7572726 Method of forming a bond pad on an I/C chip and resulting structure
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US Patent 7572735 Blanket resist to protect active side of semiconductor
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US Patent 7575954 Ceramic substrate and method of breaking same
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US Patent 7575996 Semiconductor device and method for manufacturing the same
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US Patent 7576006 Protective self-aligned buffer layers for damascene interconnects
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US Patent 7588966 Chip mounting with flowable layer
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US Patent 7588989 Dielectric multilayer structures of microelectronic devices and methods for fabricating the same
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US Patent 7589028 Hydroxyl bond removal and film densification method for oxide films using microwave post treatment
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US Patent 7592217 Capacitor with zirconium oxide and method for fabricating the same
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US Patent 7595249 Bipolar transistors with vertical structures
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US Patent 7595260 Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices
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US Patent 7595533 Thin film semiconductor device and manufacturing method
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US Patent 7605067 Method of manufacturing non-volatile memory device
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US Patent 7608497 Passivated tiered gate structure transistor and fabrication method
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US Patent 7608511 Fabrication method of trenched power MOSFET with low gate impedance
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US Patent 7608926 Nonvolatile semiconductor memory device
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US Patent 7611951 Method of fabricating MOS transistor having epitaxial region
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US Patent 7615488 Method for forming pattern, thin film transistor, display device and method for manufacturing the same, and television device
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US Patent 7618840 Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof
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US Patent 7625789 Method for manufacturing semiconductor device
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US Patent 7635644 Semiconductor device including metal interconnection and method for forming metal interconnection
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US Patent 7635645 Method for forming interconnection line in semiconductor device and interconnection line structure
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US Patent 7638347 Image sensor and method for fabricating the same
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US Patent 7655509 Silicide-silicon oxide-semiconductor antifuse device and method of making
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US Patent 7662653 Method of manufacturing a hermetic chamber with electrical feedthroughs
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US Patent 7662670 Manufacturing method of semiconductor device
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US Patent 7670906 Flash memory device
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US Patent 7675063 Liquid crystal display device and method of fabricating the same
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US Patent 7678628 Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
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US Patent 7682846 Single and double-gate pseudo-FET devices for semiconductor materials evaluation
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US Patent 7682936 Reduction in thickness of semiconductor component on substrate
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US Patent 7682954 Method of impurity introduction, impurity introduction apparatus and semiconductor device produced with use of the method
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US Patent 7682967 Method of forming metal wire in semiconductor device
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US Patent 7683447 MRAM device with continuous MTJ tunnel layers
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US Patent 7683487 Structure applied to a photolithographic process
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US Patent 7687911 Silicon-alloy based barrier layers for integrated circuit metal interconnects
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US Patent 7691677 Method of manufacturing a semiconductor device
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US Patent 7691733 Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics
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US Patent 7691738 Metal line in semiconductor device and fabricating method thereof
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US Patent 7691749 Deposition of tungsten nitride
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US Patent 7692249 End functionalization of carbon nanotubes
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US Patent 7700457 Method and zone for sealing between two microstructure substrates
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US Patent 7704852 Amorphization/templated recrystallization method for hybrid orientation substrates
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US Patent 7704873 Protective self-aligned buffer layers for damascene interconnects
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US Patent 7704876 Dual damascene interconnect structures having different materials for line and via conductors
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US Patent 7709316 Method of fabricating gate structure
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US Patent 7713837 Low temperature fusion bonding with high surface energy using a wet chemical treatment
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US Patent 7718524 Method of manufacturing semiconductor device
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US Patent 7723848 Semiconductor device and method for designing same
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US Patent 7727880 Protective self-aligned buffer layers for damascene interconnects
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US Patent 7727881 Protective self-aligned buffer layers for damascene interconnects
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US Patent 7732327 Vapor deposition of tungsten materials
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US Patent 7736925 Method of fabricating nitride-based semiconductor laser diode
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US Patent 7736975 Method for manufacturing non-volatile memory device having charge trap layer
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US Patent 7737013 Implantation of multiple species to address copper reliability
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US Patent 7737032 MOSFET structure with multiple self-aligned silicide contacts
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US Patent 7737556 Encapsulated damascene with improved overlayer adhesion
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US Patent 7741174 Methods of forming pad structures and related methods of manufacturing recessed channel transistors that include such pad structures
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US Patent 7741215 Semiconductor device and method for manufacturing the same
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US Patent 7745292 Method for fabricating a semiconductor gate structure
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US Patent 7745298 Method of forming a via
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US Patent 7749788 Manufacturing method of photoelectric conversion device
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US Patent 7754580 Method for manufacturing semiconductor substrate
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US Patent 7759243 Method for forming an on-chip high frequency electro-static discharge device
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US Patent 7763544 Method of forming fine pattern of semiconductor device using sige layer as sacrificial layer, and method of forming self-aligned contacts using the same
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US Patent 7767513 Method of manufacturing semiconductor device and semiconductor device
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US Patent 7767558 Method of crystallizing amorphous silicon and device fabricated using the same
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US Patent 7776685 Copolymers, polymer resin composition for buffer layer method of forming a pattern using the same and method of manufacturing a capacitor using the same
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US Patent 7777342 Semiconductor device and method for manufacturing the same
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US Patent 7781279 Method for manufacturing a memory
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US Patent 7781281 Method of fabricating self-aligned contact pad using chemical mechanical polishing process
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US Patent 7785954 Semiconductor memory integrated circuit and its manufacturing method
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US Patent 7785970 Method of forming source and drain regions utilizing dual capping layers and split thermal processes
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US Patent 7786468 Layer transfer of low defect SiGe using an etch-back process
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US Patent 7786487 Semiconductor device and manufacturing method thereof
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US Patent 7790531 Methods for isolating portions of a loop of pitch-multiplied material and related structures
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US Patent 7795129 Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment
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US Patent 7799608 Die stacking apparatus and method
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US Patent 7803672 Thin film transistor array panel and method of manufacturing the same
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US Patent 7825031 Method of fabricating a semiconductor device
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US Patent 7825033 Methods of forming variable resistance memory cells, and methods of etching germanium, antimony, and tellurium-comprising materials
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US Patent 7829456 Method to modulate coverage of barrier and seed layer using titanium nitride
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US Patent 7833833 Method of manufacturing a semiconductor device
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US Patent 7838366 Method for fabricating a metal gate structure
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US Patent 7842562 Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates
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US Patent 7842611 Substrate and manufacturing method of the same
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US Patent 7842988 Manufacturing method of photoelectric conversion device
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US Patent 7846835 Contact barrier layer deposition process
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US Patent 7851346 Bonding metallurgy for three-dimensional interconnect
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US Patent 7863194 Implantation of multiple species to address copper reliability
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US Patent 7867818 Methods and apparatuses for providing stacked-die devices
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US Patent 7867825 Semiconductor die with protective layer and related method of processing a semiconductor wafer
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US Patent 7867878 Stacked semiconductor chips
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US Patent 7883929 Methods of manufacturing non-volatile memory devices by implanting metal ions into grain boundaries of variable resistance layers
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US Patent 7884016 Liner materials and related processes for 3-D integration
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US Patent 7888264 MOSFET structure with multiple self-aligned silicide contacts
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US Patent 7892913 Method of manufacturing semiconductor device and semiconductor device
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US Patent 7892932 Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure
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US Patent 7893469 Image sensor and method for fabricating the same
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US Patent 7897448 Formation of high voltage transistor with high breakdown voltage
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US Patent 7897450 Method for encapsulating a high-K gate stack by forming a liner at two different process temperatures
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US Patent 7902018 Fluorine plasma treatment of high-k gate stack for defect passivation
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US Patent 7902019 Dielectric layer for semiconductor device and method of manufacturing the same
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US Patent 7902043 Method of producing bonded wafer
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US Patent 7910409 Bi-directional transistor with by-pass path and method therefor
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US Patent 7910430 NAND flash memory device and method of manufacturing the same
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US Patent 7910478 Method of manufacturing semiconductor devices
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US Patent 7915095 Silicide-silicon oxide-semiconductor antifuse device and method of making
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US Patent 7915685 Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates
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US Patent 7919367 Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process
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US Patent 7923758 Method and apparatus for producing gallium arsenide and silicon composites and devices incorporating same
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US Patent 7923776 Trench-gate field effect transistor with channel enhancement region and methods of forming the same
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US Patent 7936012 Recessed channel transistors that include pad structures
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US Patent 7943514 Integrated circuits having TSVs including metal gettering dielectric liners
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US Patent 7947564 Method of fabricating a mixed microtechnology structure and a structure obtained thereby
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US Patent 7951706 Method of manufacturing metal interconnection
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US Patent 7951719 Self-masking defect removing method
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US Patent 7952148 Method of manufacturing semiconductor device and semiconductor device
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US Patent 7955977 Method of light induced plating on semiconductors
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US Patent 7960236 Phosphorus containing Si epitaxial layers in N-type source/drain junctions
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US Patent 7960263 Amorphization/templated recrystallization method for hybrid orientation substrates
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US Patent 7964919 Thin film resistors integrated at two different metal single die
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US Patent 7968392 Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate
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US Patent 7968443 Cross-contamination control for processing of circuits comprising MOS devices that include metal comprising high-K dielectrics
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US Patent 7969020 Die stacking apparatus and method
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US Patent 7972924 Method for manufacturing a memory
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US Patent 7981815 Semiconductor device producing method and substrate processing apparatus
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US Patent 7985685 Method of manufacturing semiconductor device
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US Patent 7994039 Method of fabricating semiconductor device
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US Patent 7998860 Method for fabricating semiconductor components using maskless back side alignment to conductive vias
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US Patent 7998880 Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties
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US Patent 8003516 BEOL interconnect structures and related fabrication methods
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US Patent 8008151 Shallow source MOSFET
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US Patent 8008185 Semiconductor devices and methods of forming the same
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US Patent 8012822 Process for forming dielectric films
Edits on 13 Dec, 2021
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Golden AI
edited on 13 Dec, 2021
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Patent primary examiner of
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US Patent 8012822 Process for forming dielectric films
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 8008185 Semiconductor devices and methods of forming the same
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
‌
US Patent 8008151 Shallow source MOSFET
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
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Patent primary examiner of
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US Patent 8003516 BEOL interconnect structures and related fabrication methods
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Golden AI
edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7994039 Method of fabricating semiconductor device
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
‌
US Patent 7985685 Method of manufacturing semiconductor device
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
‌
US Patent 7981815 Semiconductor device producing method and substrate processing apparatus
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7972924 Method for manufacturing a memory
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7969020 Die stacking apparatus and method
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edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7964919 Thin film resistors integrated at two different metal single die
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Golden AI
edited on 7 Dec, 2021
Edits made to:
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Patent primary examiner of
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US Patent 7960263 Amorphization/templated recrystallization method for hybrid orientation substrates
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
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Patent primary examiner of
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US Patent 7960236 Phosphorus containing Si epitaxial layers in N-type source/drain junctions
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
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Patent primary examiner of
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US Patent 7955977 Method of light induced plating on semiconductors

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