Patent attributes
Methods of fabricating MOSFETs in semiconductor/r devices are disclosed. One example method may include forming an isolation layer on a semiconductor substrate and forming a capping layer thereon, forming an epitaxial active region which is not covered with the isolation layer on said semiconductor substrate by using selectively epitaxial growth, and forming a gate dielectric layer and a gate electrode on said epitaxial active region, sequentially. The example method may also include forming a source/drain plug spaced apart from the both sides of said gate electrode in said epitaxial active region, forming a source/drain into said epitaxial active region on which said source/drain plug is formed, forming an interlayer dielectric layer on the entire surface of the resultant structure after the source/drain is formed; and forming contacts in said interlayer dielectric layer, wherein said contacts are connected to said gate electrode and said source/drain plug, respectively.
