Patent attributes
A method for fabricating a power MOSFET, comprising an epitaxial layer, a gate dielectric layer and a gate layer formed on a substrate, the gate dielectric layer and the gate layer defined to form a gate structure, a stacked mask and the surface of the epitaxial layer partially exposed between the gate structure and the stacked mask, a well region formed in the epitaxial layer and partially under the gate structure and the stacked mask, a source region is formed in the well region between the gate structure and the stacked mask, a patterned dielectric layer exposing the top of the stacked mask formed over the substrate, the stacked mask removed to form a contact opening exposing the surface of the well region partially and a body region formed in the well region under the contact opening.
