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Thanh Nguyen

based in Massachusetts

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Edits on 20 Aug, 2022
"Infobox creation from: https://twitter.com/nguyenthanhmd"
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Golden AI
edited on 20 Aug, 2022
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Location
Boston
Boston
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godwinno feliks
edited on 20 Aug, 2022
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Twitter URL
https://twitter.com/nguyenthanhmd
Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7087961 Semiconductor device with reduced on-state resistance
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US Patent 7087996 Etchant formulation for selectively removing thin films in the presence of copper, tin, and lead
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US Patent 7091123 Method of forming metal wiring line including using a first insulating film as a stopper film
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US Patent 7094626 Method for encapsulating an electrical component
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US Patent 7098055 Apparatus and method for testing defects
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US Patent 7098087 Manufacturing method of semiconductor device
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US Patent 7101796 Method for forming a plane structure
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US Patent 7101798 Method to modulate etch rate in SLAM
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US Patent 7105446 Apparatus for pre-conditioning CMP polishing pad
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US Patent 7109553 Semiconductor device and method of manufacturing same
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US Patent 7112503 Enhanced surface area capacitor fabrication methods
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US Patent 7115510 Method for electrochemically processing a workpiece
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US Patent 7125793 Method for forming an opening for an interconnect structure in a dielectric layer having a photosensitive material
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US Patent 7129139 Methods for selective deposition to improve selectivity
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US Patent 7129157 Method for fabricating an integrated circuit
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US Patent 7129171 Selective oxygen-free etching process for barrier materials
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US Patent 7132348 Low k interconnect dielectric using surface transformation
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US Patent 7132363 Stabilizing fluorine etching of low-k materials
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US Patent 7135366 Method for fabricating a lateral metal-insulator-metal capacitor
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US Patent 7135388 Method for fabricating single crystal silicon film
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US Patent 7144794 Ion source, ion implanting device, and manufacturing method of semiconductor devices
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US Patent 7144796 Method of fabricating semiconductor components through implantation and diffusion in a semiconductor substrate
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US Patent 7148138 Method of forming contact hole and method of manufacturing semiconductor device
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US Patent 7153747 Method for making a transistor on a SiGe/SOI substrate
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US Patent 7153776 Method for reducing amine based contaminants
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US Patent 7157777 Semiconductor device including silicided source and drain electrodes
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US Patent 7160784 Method of manufacturing a semiconductor film with little warp
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US Patent 7163876 Method for manufacturing group-III nitride compound semiconductor, and group-III nitride compound semiconductor device
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US Patent 7164178 Semiconductor device and method for manufacturing the same
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US Patent 7169652 Method of manufacturing electro-optical device, electro-optical device, transferred chip, transfer origin substrate
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US Patent 7169706 Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition
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US Patent 7172961 Method of fabricating an interconnect structure having reduced internal stress
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US Patent 7176146 Method of making a molecule-surface interface
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US Patent 7180194 Semiconductor device with multi-staged cut side surfaces
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US Patent 7183184 Method for making a semiconductor device that includes a metal gate electrode
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US Patent 7183189 Semiconductor device, circuit board, and electronic instrument
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US Patent 7192812 Method for manufacturing electro-optical substrate
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US Patent 7192835 Method of forming a high-k film on a semiconductor device
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US Patent 7202170 Method of improving etching profile of floating gates for flash memory devices
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US Patent 7202177 Nitrous oxide stripping process for organosilicate glass
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US Patent 7205218 Method including forming gate dielectrics having multiple lanthanide oxide layers
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US Patent 7205235 Method for reducing corrosion of metal surfaces during semiconductor processing
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US Patent 7214551 Multiple gate electrode linewidth measurement and photoexposure compensation method
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US Patent 7217650 Metallic nanowire interconnections for integrated circuit fabrication
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US Patent 7226853 Method of forming a dual damascene structure utilizing a three layer hard mask structure
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US Patent 7229890 Forming integrated circuits using selective deposition of undoped silicon film seeded in chlorine and hydride gas
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US Patent 7229936 Method to reduce photoresist pattern collapse by controlled surface microroughening
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US Patent 7232728 High quality oxide on an epitaxial layer
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US Patent 7232732 Semiconductor device with a toroidal-like junction
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US Patent 7232752 Method of removing contaminants from a silicon wafer after chemical-mechanical polishing operation
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US Patent 7233040 Semiconductor device contains a Pb
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US Patent 7235502 Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors
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US Patent 7235884 Local control of electrical and mechanical properties of copper interconnects to achieve stable and reliable via
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US Patent 7241661 Method of forming a coupling dielectric Ta
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US Patent 7247553 Method of manufacturing a semiconductor device
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US Patent 7253079 Coplanar mounting member for a MEM sensor
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US Patent 7256418 Polythiophenes and devices thereof
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US Patent 7259029 Method of forming protective structure for active matrix triode field emission device
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US Patent 7264983 Method of enhancing connection strength for suspended membrane leads and substrate contacts
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US Patent 7271014 Fabrication method of semiconductor integrated circuit device including inspecting using probe card
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US Patent 7271082 Method of manufacturing a semiconductor device
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US Patent 7273782 Method for manufacturing and operating a non-volatile memory
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US Patent 7282737 Projector including a light source and liquid crystal display device
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US Patent 7282766 Fin-type semiconductor device with low contact resistance
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US Patent 7285814 Dynamic random access memory circuitry and integrated circuitry
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US Patent 7291528 Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions
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US Patent 7294550 Method of fabricating metal oxide semiconductor device
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US Patent 7294569 Semiconductor device fabrication method and semiconductor device fabrication system for minimizing film-thickness variations
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US Patent 7297610 Method of segmenting a wafer
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US Patent 7303954 Method for manufacturing NAND flash device
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US Patent 7304367 Metal-insulator-metal capacitors including transition metal silicide films on doped polysilicon contact plugs
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US Patent 7312115 Fabrication method for a semiconductor structure having integrated capacitors
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US Patent 7312149 Copper plating of semiconductor devices using single intermediate low power immersion step
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US Patent 7314783 Method of fabricating contact line of liquid crystal display device
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US Patent 7319054 Method of fabricating liquid crystal display device
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US Patent 7320912 Trench capacitors with buried isolation layer formed by an oxidation process and methods for manufacturing the same
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US Patent 7326585 Forming process of thin film pattern and manufacturing process of device, electro-optical apparatus and electronic apparatus
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US Patent 7326612 Method for fabricating a semiconductor structure
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US Patent 7332397 Method for fabricating semiconductor device
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US Patent 7335541 Method for fabricating thin film transistor using the mask for forming polysilicon including slit patterns deviated from each other
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US Patent 7338872 Method of depositing a layer of a material on a substrate
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US Patent 7345358 Copper interconnect for semiconductor device
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US Patent 7351611 Method of making the mould for encapsulating a leadframe package
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US Patent 7358186 Method and apparatus for material deposition in semiconductor fabrication
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US Patent 7368333 Semiconductor device and method of manufacturing the same by using atomic layer deposition
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US Patent 7371675 Method and apparatus for bonding a wire
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US Patent 7378344 Method of manufacturing a semiconductor device including a silicide layer having an NiSi phase provided on source and drain regions
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US Patent 7381602 Method of forming a field effect transistor comprising a stressed channel region
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US Patent 7390709 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
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US Patent 7390732 Method for producing a semiconductor device with pyramidal bump electrodes bonded onto pad electrodes arranged on a semiconductor chip
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US Patent 7393779 Shrinking contact apertures through LPD oxide
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US Patent 7396710 Fin-type semiconductor device with low contact resistance and its manufacture method
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US Patent 7396714 Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions
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US Patent 7399696 Method for high performance inductor fabrication using a triple damascene process with copper BEOL
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US Patent 7402519 Interconnects having sealing structures to enable selective metal capping layers
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US Patent 7407839 Method of manufacturing active matrix substrate with height control member
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US Patent 7410865 Method for fabricating capacitor of semiconductor device
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US Patent 7413983 Plating method including pretreatment of a surface of a base metal
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US Patent 7416968 Methods of forming field effect transistors having metal silicide gate electrodes
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US Patent 7417319 Semiconductor device with connecting via and dummy via and method of manufacturing the same
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US Patent 7425485 Method for forming microelectronic assembly
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US Patent 7429517 CMOS transistor using high stress liner layer
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US Patent 7429538 Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric
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US Patent 7432152 Methods of forming HSG layers and devices
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US Patent 7432201 Hybrid PVD-CVD system
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US Patent 7432203 Methods for fabricating a metal layer pattern
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US Patent 7439093 Method of making a MEMS device containing a cavity with isotropic etch followed by anisotropic etch
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US Patent 7439186 Method for structuring a silicon layer
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US Patent 7439607 Beta control using a rapid thermal oxidation
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US Patent 7442598 Method of forming an interlayer dielectric
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US Patent 7445978 Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS
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US Patent 7446005 Manufacturable recessed strained RSD structure and process for advanced CMOS
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US Patent 7446408 Semiconductor package with heat sink
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US Patent 7452794 Manufacturing method of a thin film semiconductor device
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US Patent 7462571 Film formation method and apparatus for semiconductor process for forming a silicon nitride film
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US Patent 7465626 Method for forming a high-k dielectric stack
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US Patent 7473570 Method for forming epitaxial layers of gallium nitride-based compound semiconductors
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US Patent 7473655 Method for silicon based dielectric chemical vapor deposition
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US Patent 7476573 Methods of selective deposition of fine particles onto selected regions of a substrate
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US Patent 7479676 Transistor of semiconductor memory device
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US Patent 7488633 Method for forming polysilicon by illuminating a laser beam at the amorphous silicon substrate through a mask
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US Patent 7488648 Methods of fabricating scalable two-transistor memory devices having metal source/drain regions
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US Patent 7489041 Copper interconnect
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US Patent 7491578 Method of forming crack trapping and arrest in thin film structures
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US Patent 7501293 Semiconductor device in which zinc oxide is used as a semiconductor material and method for manufacturing the semiconductor device
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US Patent 7501650 P-type semiconductor carbon nanotube using halogen element and fullerene or alkali element
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US Patent 7501706 Semiconductor devices to reduce stress on a metal interconnect
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US Patent 7507596 Method of fabricating a high quantum efficiency photodiode
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US Patent 7507597 Method for fabricating CMOS image sensor
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US Patent 7510907 Through-wafer vias and surface metallization for coupling thereto
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US Patent 7511363 Copper interconnect
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US Patent 7514281 Method for manufacturing organic electroluminescence device and electronic apparatus
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US Patent 7514708 80 nanometer diameter resonant tunneling diode with improved peak-to-valley ratio
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US Patent 7517759 Method of fabricating metal oxide semiconductor device
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US Patent 7517801 Method for selectivity control in a plasma processing system
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US Patent 7521362 Methods for the optimization of ion energy control in a plasma processing system
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US Patent 7521796 Method of making the semiconductor device, circuit board, and electronic instrument
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US Patent 7525196 Protection of seedlayer for electroplating
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US Patent 7528006 Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion
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US Patent 7531408 Method of manufacturing a semiconductor device containing a Pb
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US Patent 7541241 Method for fabricating memory cell
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US Patent 7541618 Liquid crystal device having a thin film transistor
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US Patent 7544563 Methods of forming a plurality of capacitors
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US Patent 7544606 Method to implement stress free polishing
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US Patent 7547917 Inverted multilayer semiconductor device assembly
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US Patent 7550794 Micromechanical systems device comprising a displaceable electrode and a charge-trapping layer
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US Patent 7553769 Method for treating a dielectric film
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US Patent 7563655 Method of fabricating the liquid crystal display device
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US Patent 7563673 Method of forming gate structure of semiconductor device
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US Patent 7563704 Method of forming an interconnect including a dielectric cap having a tensile stress
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US Patent 7569934 Copper interconnect
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US Patent 7572732 Method to modulate etch rate in SLAM
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US Patent 7573130 Crack trapping and arrest in thin film structures
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US Patent 7575956 Fabrication method for semiconductor package heat spreaders
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US Patent 7575997 Method for forming contact hole of semiconductor device
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US Patent 7576441 Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device
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US Patent 7582538 Method of overlay measurement for alignment of patterns in semiconductor manufacturing
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US Patent 7588962 Method of making semiconductor device
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US Patent 7588977 Method of fabricating a MOS field effect transistor having plurality of channels
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US Patent 7592246 Method and semiconductor device having copper interconnect for bonding
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US Patent 7598141 Method of fabricating static random access memory
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US Patent 7602071 Apparatus for dividing an adhesive film mounted on a wafer
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US Patent 7605023 Manufacturing method for a semiconductor device and heat treatment method therefor
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US Patent 7612438 Active matrix substrate with height control member
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US Patent 7618854 High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same
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US Patent 7629240 Controlling dopant diffusion in a semiconductor region
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US Patent 7642177 Method of manufacturing nanowire
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US Patent 7642196 Semiconductor fabrication processes
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US Patent 7655561 Method for making an opening for electrical contact by etch back profile control
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US Patent 7670878 Method for manufacturing semiconductor package
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US Patent 7678595 Method for forming a light emitting apparatus
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US Patent 7687287 Method for fabricating a polymer L.E.D.
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US Patent 7687908 Thin film electrode for high-quality GaN optical devices
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US Patent 7691692 Substrate processing apparatus and a manufacturing method of a thin film semiconductor device
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US Patent 7696538 Sensor for measuring liquid contaminants in a semiconductor wafer fabrication process
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US Patent 7704833 Method of forming abrupt source drain metal gate transistors
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US Patent 7709280 Semiconductor laser with narrow beam divergence
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US Patent 7709933 Structural element having a porous region at least regionally provided with a cover layer and its use as well as method for setting the thermal conductivity of a porous region
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US Patent 7718532 Method of forming a high-k film on a semiconductor device
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US Patent 7723162 Method for producing shock and tamper resistant microelectronic devices
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US Patent 7723821 Microelectronic assembly
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US Patent 7727878 Method for forming passivation layer
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US Patent 7732251 Method of making a semiconductor device having a multicomponent oxide
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US Patent 7732317 Methods of forming contact structures for memory cells using both anisotropic and isotropic etching
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US Patent 7834405 Semiconductor device including I/O oxide and nitrided core oxide on substrate
Edits on 6 Dec, 2021
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Golden AI
edited on 6 Dec, 2021
Edits made to:
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Patent primary examiner of
‌
US Patent 7834405 Semiconductor device including I/O oxide and nitrided core oxide on substrate
Edits on 4 Dec, 2021
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Golden AI
edited on 4 Dec, 2021
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7732251 Method of making a semiconductor device having a multicomponent oxide
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7727878 Method for forming passivation layer
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7723821 Microelectronic assembly
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7723162 Method for producing shock and tamper resistant microelectronic devices
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7718532 Method of forming a high-k film on a semiconductor device
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7709280 Semiconductor laser with narrow beam divergence
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7704833 Method of forming abrupt source drain metal gate transistors
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7696538 Sensor for measuring liquid contaminants in a semiconductor wafer fabrication process
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits on 4 Dec, 2021
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7687908 Thin film electrode for high-quality GaN optical devices
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7687287 Method for fabricating a polymer L.E.D.
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7678595 Method for forming a light emitting apparatus
Golden AI profile picture
Golden AI
edited on 4 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7670878 Method for manufacturing semiconductor package
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Golden AI
edited on 3 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7655561 Method for making an opening for electrical contact by etch back profile control

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