US Patent 7172961 Method of fabricating an interconnect structure having reduced internal stress

A copper damascene process is provided. A semiconductor substrate having a base dielectric layer thereon is prepared. A first damascened copper interconnect structure is formed in the base dielectric layer. The first damascened copper interconnect structure is capped with a dielectric barrier; Subsequently, multiple chemical vapor deposition (CVD) cycles within a CVD reactor is carried out to deposit a low-k dielectric film stack on the first dielectric barrier until thickness of the low-k dielectric film stack reaches a desired value, wherein each of the CVD cycles comprises: (1) chemical vapor depositing a low-k dielectric film having a pre-selected thickness; and (2) cooling down the low-k dielectric film within the CVD reactor. A second damascened copper interconnect structure is formed in the low-k dielectric film stack.