Patent attributes
A method is provided for fabricating a semiconductor structure, such as a DRAM memory cell, that includes an elevated region with at least one sidewall. The at least one sidewall is provided with an insulation layer. A mask layer is applied to the insulation layer. The mask layer is patterned in such a way that it is removed from the surface of the elevated region and from an edge region of the insulation layer, said edge region adjoining the sidewall of the elevated region. A material is implanted into the surface of the elevated region and also into the edge region of the insulation layer. The material preferably alters the properties of the surface of the elevated region and also increases the etching rate of the insulation layer. The mask layer is removed and the insulation layer is subjected to a whole-area etching step.
