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Asok Kumar Sarkar

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Edits on 14 Dec, 2021
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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7091563 Method and structure for improved MOSFETs using poly/silicide gate height control
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US Patent 7098068 Method of forming a chalcogenide material containing device
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US Patent 7098154 Method for fabricating semiconductor device and semiconductor device
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US Patent 7101814 Masking without photolithography during the formation of a semiconductor device
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US Patent 7105461 Composite dielectric forming methods and composite dielectrics
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US Patent 7109073 Method for fabricating semiconductor device
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US Patent 7109581 System and method using self-assembled nano structures in the design and fabrication of an integrated circuit micro-cooler
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US Patent 7112843 Semiconductor device with low resistance region
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US Patent 7112851 Field effect transistor with electroplated metal gate
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US Patent 7112861 Magnetic tunnel junction cap structure and method for forming the same
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US Patent 7115489 Methods of growing epitaxial silicon
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US Patent 7115531 Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices
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US Patent 7118989 Method of forming vias on a wafer stack using laser ablation
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US Patent 7122389 Method for processing semiconductor devices in a singulated form
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US Patent 7122488 High density plasma process for the formation of silicon dioxide on silicon carbide substrates
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US Patent 7122489 Manufacturing method of composite sheet material using ultrafast laser pulses
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US Patent 7122895 Stud-cone bump for probe tips used in known good die carriers
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US Patent 7125790 Inclusion of low-k dielectric material between bit lines
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US Patent 7125799 Method and device for processing substrate, and apparatus for manufacturing semiconductor device
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US Patent 7126228 Apparatus for processing semiconductor devices in a singulated form
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US Patent 7129154 Method of growing semiconductor nanowires with uniform cross-sectional area using chemical vapor deposition
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US Patent 7129161 Depositing a tantalum film
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US Patent 7129183 Method of forming grating microstrutures by anodic oxidation
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US Patent 7129553 Lanthanide oxide/hafnium oxide dielectrics
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US Patent 7132299 Method of forming a magnetic random access memory structure
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US Patent 7132351 Method of fabricating a compound semiconductor layer
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US Patent 7135345 Methods for processing semiconductor devices in a singulated form
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US Patent 7135391 Polycrystalline SiGe junctions for advanced devices
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US Patent 7135762 Semiconductor device, stacked semiconductor device, methods of manufacturing them, circuit board, and electronic instrument
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US Patent 7138285 Control of contact resistance in quantum well intermixed devices
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US Patent 7141491 Method for fabricating a semiconductor device
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US Patent 7141513 Integrated ashing and implant annealing method using ozone
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US Patent 7145183 Method for producing a vertically emitting laser
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US Patent 7148118 Methods of forming metal nitride, and methods of forming capacitor constructions
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US Patent 7148124 Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers
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US Patent 7148128 Electronically addressable microencapsulated ink and display thereof
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US Patent 7148518 Group-III nitride semiconductor stack, method of manufacturing the same, and group-III nitride semiconductor device
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US Patent 7151038 Semiconductor device having an integral resistance element
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US Patent 7153719 Method of fabricating a storage gate pixel design
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US Patent 7154178 Multilayer diffusion barrier for copper interconnections
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US Patent 7157288 Method of producing ferroelectric capacitor
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US Patent 7160752 Fabrication of advanced silicon-based MEMS devices
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US Patent 7160791 Batch process and device for forming spacer structures for packaging optical reflection devices
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US Patent 7169700 Metal interconnect features with a doping gradient
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US Patent 7169717 Method of producing a calibration wafer
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US Patent 7176528 Glass-based SOI structures
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US Patent 7179719 System and method for hydrogen exfoliation
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US Patent 7183177 Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
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US Patent 7186634 Method for forming metal single-layer film, method for forming wiring, and method for producing field effect transistors
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US Patent 7187042 Backgated FinFET having different oxide thicknesses
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US Patent 7189660 Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device
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US Patent 7190024 Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method
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US Patent 7192844 Glass-based SOI structures
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US Patent 7192854 Method of plasma doping
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US Patent 7192859 Method of manufacturing semiconductor device and display device
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US Patent 7193295 Process and apparatus for thinning a semiconductor workpiece
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US Patent 7196012 Methods for planarization of dielectric layer around metal patterns for optical efficiency enhancement
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US Patent 7196020 Method for PECVD deposition of selected material films
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US Patent 7199004 Method of forming capacitor of semiconductor device
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US Patent 7202149 Semiconductor device and manufacturing method thereof
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US Patent 7205220 Gallium nitride based III-V group compound semiconductor device and method of producing the same
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US Patent 7208401 Method for forming a thin film
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US Patent 7208428 Method and apparatus for treating article to be treated
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US Patent 7211499 Methods of forming silicon dioxide layers, and methods of forming trench isolation regions
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US Patent 7211503 Electronic devices fabricated by use of random connections
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US Patent 7211523 Method for forming field oxide
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US Patent 7211525 Hydrogen treatment enhanced gap fill
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US Patent 7211855 Intermediate semiconductor device structure including multiple photoresist layers
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US Patent 7217639 Method of manufacturing a material compound wafer
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US Patent 7217662 Method of processing a substrate
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US Patent 7220609 Method of manufacturing a semiconductor structure comprising clusters and/or nanocrystal of silicon and a semiconductor structure of this kind
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US Patent 7220652 Metal-insulator-metal capacitor and interconnecting structure
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US Patent 7223630 Low stress semiconductor device coating and method of forming thereof
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US Patent 7224031 Semiconductor wafer and manufacturing method thereof
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US Patent 7226819 Methods for forming wiring and manufacturing thin film transistor and droplet discharging method
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US Patent 7227262 Manufacturing method for semiconductor device and semiconductor device
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US Patent 7235474 System and method for imprint lithography to facilitate dual damascene integration with two imprint acts
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US Patent 7235843 Implanting carbon to form P-type source drain extensions
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US Patent 7238567 System and method for integrating low schottky barrier metal source/drain
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US Patent 7238594 Controlled nanowire growth in permanent, integrated nano-templates and methods of fabricating sensor and transducer structures
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US Patent 7244671 Methods of forming conductive structures including titanium-tungsten base layers and related structures
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US Patent 7247552 Integrated circuit having structural support for a flip-chip interconnect pad and method therefor
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US Patent 7250364 Semiconductor devices with composite etch stop layers and methods of fabrication thereof
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US Patent 7253070 Transistor structure with minimized parasitics and method of fabricating the same
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US Patent 7253093 Method for fabricating interconnection in an insulating layer on a wafer
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US Patent 7253512 Organic dielectric electronic interconnect structures and method for making
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US Patent 7256109 Isotropic polycrystalline silicon
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US Patent 7259093 Methods of forming a conductive contact through a dielectric
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US Patent 7259391 Vertical interconnect for organic electronic devices
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US Patent 7262114 Die attaching method of semiconductor chip using warpage prevention material
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US Patent 7268038 Method for fabricating a MIM capacitor having increased capacitance density and related structure
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US Patent 7268053 Semiconductor wafer and a method for manufacturing a semiconductor wafer
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US Patent 7268377 Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices
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US Patent 7271483 Bump structure of semiconductor package and method for fabricating the same
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US Patent 7273819 Method and apparatus for processing semiconductor substrates
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US Patent 7279406 Tailoring channel strain profile by recessed material composition control
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US Patent 7279733 Dual damascene interconnection with metal-insulator-metal-capacitor and method of fabricating the same
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US Patent 7282421 Methods for reducing a thickness variation of a nitride layer formed in a shallow trench isolation CMP process and for forming a device isolation film of a semiconductor device
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US Patent 7282779 Device, method of manufacture thereof, manufacturing method for active matrix substrate, electro-optical apparatus and electronic apparatus
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US Patent 7288420 Method for manufacturing an electro-optical device
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US Patent 7288488 Method for resist strip in presence of regular low k and/or porous low k dielectric materials
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US Patent 7294898 Field effect transistor having source and/or drain forming Schottky or Schottky-like contact with strained semiconductor substrate
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US Patent 7297611 Method for producing thin layers of semiconductor material from a donor wafer
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US Patent 7297612 Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes
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US Patent 7297613 Method of fabricating and integrating high quality decoupling capacitors
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US Patent 7301193 Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell
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US Patent 7307306 Etch mask and method of forming a magnetic random access memory structure
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US Patent 7312091 Methods for forming a ferroelectric layer and capacitor and FRAM using the same
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US Patent 7314828 Repairing method for low-k dielectric materials
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US Patent 7319268 Semiconductor device having capacitors for reducing power source noise
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US Patent 7320921 Smart grading implant with diffusion retarding implant for making integrated circuit chips
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US Patent 7323398 Method of layer transfer comprising sequential implantations of atomic species
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US Patent 7326644 Semiconductor device and method of fabricating the same
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US Patent 7332444 Method for smoothing areas in structures by utilizing the surface tension
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US Patent 7332446 Composition for forming porous film, porous film and method for forming the same, interlevel insulator film and semiconductor device
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US Patent 7335545 Control of strain in device layers by prevention of relaxation
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US Patent 7338883 Process for transferring a layer of strained semiconductor material
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US Patent 7341900 Semiconductor device and method for manufacturing the same
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US Patent 7341928 System and process for processing a plurality of semiconductor thin films which are crystallized using sequential lateral solidification techniques
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US Patent 7344971 Manufacturing method of semiconductor device
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US Patent 7348650 Element having microstructure and manufacturing method thereof
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US Patent 7354868 Methods of fabricating a semiconductor device using a dilute aqueous solution of an ammonia and peroxide mixture
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US Patent 7358194 Sequential deposition process for forming Si-containing films
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US Patent 7368317 Method of producing an N-type diamond with high electrical conductivity
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US Patent 7368383 Hillock reduction in copper films
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US Patent 7371666 Process for producing luminescent silicon nanoparticles
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US Patent 7374963 Technique and apparatus for depositing thin layers of semiconductors for solar cell fabrication
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US Patent 7375014 Methods of electrochemically treating semiconductor substrates
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US Patent 7375025 Method for forming a metal silicide layer in a semiconductor device
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US Patent 7375383 Gallium nitride based III-V group compound semiconductor device and method of producing the same
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US Patent 7384867 Formation of composite tungsten films
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US Patent 7387939 Methods of forming semiconductor structures and capacitor devices
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US Patent 7393707 Method for manufacturing an electro-optical device
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US Patent 7393729 Method for fabricating semiconductor device
Edits on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
Edits made to:
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Infobox
Patent primary examiner of
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US Patent 7393729 Method for fabricating semiconductor device
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7393707 Method for manufacturing an electro-optical device
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7387939 Methods of forming semiconductor structures and capacitor devices
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7384867 Formation of composite tungsten films
Edits on 29 Nov, 2021
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Golden AI
edited on 29 Nov, 2021
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Golden AI
edited on 29 Nov, 2021
Edits made to:
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Infobox
Patent primary examiner of
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US Patent 7375025 Method for forming a metal silicide layer in a semiconductor device
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Golden AI
edited on 29 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7375014 Methods of electrochemically treating semiconductor substrates
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Golden AI
edited on 29 Nov, 2021
Edits on 26 Nov, 2021
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7371666 Process for producing luminescent silicon nanoparticles
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368383 Hillock reduction in copper films
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368317 Method of producing an N-type diamond with high electrical conductivity
Edits on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7358194 Sequential deposition process for forming Si-containing films
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Golden AI
edited on 25 Nov, 2021
Edits on 24 Nov, 2021
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Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7348650 Element having microstructure and manufacturing method thereof
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Golden AI
edited on 24 Nov, 2021
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Infobox
Patent primary examiner of
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US Patent 7344971 Manufacturing method of semiconductor device
Edits on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
Edits made to:
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Infobox
Patent primary examiner of
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US Patent 7341900 Semiconductor device and method for manufacturing the same
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7338883 Process for transferring a layer of strained semiconductor material
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7335545 Control of strain in device layers by prevention of relaxation

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