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Alexander Oscar Williams

founder of Coffee Stain Studios

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Edits on 17 Feb, 2022
"update inverses"
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Golden AI
edited on 17 Feb, 2022
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Founder of
Coffee Stain Studios
Coffee Stain Studios
Edits on 14 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7088003 Structures and methods for integration of ultralow-k dielectrics with improved reliability
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US Patent 7091588 Semiconductor device including primary and secondary side circuits on first and second substrates with capacitive insulation
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US Patent 7095098 Electrically isolated and thermally conductive double-sided pre-packaged component
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US Patent 7095101 Supporting frame for surface-mount diode package
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US Patent 7095104 Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same
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US Patent 7098528 Embedded redistribution interposer for footprint compatible chip package conversion
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US Patent 7098544 Edge seal for integrated circuit chips
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US Patent 7102217 Interposer substrates with reinforced interconnect slots, and semiconductor die packages including same
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US Patent 7105928 Copper wiring with high temperature superconductor (HTS) layer
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US Patent 7112883 Semiconductor device with temperature control mechanism
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US Patent 7115984 Semiconductor devices including peripherally located bond pads, intermediates thereof, assemblies, and packages including the semiconductor devices, and support elements for the semiconductor devices
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US Patent 7115988 Bypass capacitor embedded flip chip package lid and stiffener
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US Patent 7119435 Semiconductor device with source/drain extension layer
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US Patent 7122850 Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current
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US Patent 7129583 Multi-chip package structure
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US Patent 7132736 Devices having compliant wafer-level packages with pillars and methods of fabrication
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US Patent 7132746 Electronic assembly with solder-bonded heat sink
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US Patent 7132752 Semiconductor chip and semiconductor device including lamination of semiconductor chips
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US Patent 7132753 Stacked die assembly having semiconductor die overhanging support
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US Patent 7135703 Test tray with carrier modules for a semiconductor device handler
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US Patent 7135754 Chip type solid electrolytic capacitor having a small size and a simple structure
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US Patent 7135770 Semiconductor element with conductive columnar projection and a semiconductor device with conductive columnar projection
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US Patent 7135777 Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof
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US Patent 7138707 Semiconductor package including leads and conductive posts for providing increased functionality
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US Patent 7138708 Electronic system for fixing power and signal semiconductor chips
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US Patent 7138723 Deformable semiconductor device
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US Patent 7145226 Scalable microelectronic package using conductive risers
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US Patent 7148535 Zero capacitance bondpad utilizing active negative capacitance
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US Patent 7148554 Discrete electronic component arrangement including anchoring, thermally conductive pad
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US Patent 7148564 Dual-sided substrate integrated circuit package including a leadframe having leads with increased thickness
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US Patent 7148578 Semiconductor multi-chip package
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US Patent 7157794 Semiconductor device that suppresses variations in high frequency characteristics of circuit elements
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US Patent 7161237 Flip chip packaging using recessed interposer terminals
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US Patent 7164198 Multilayered substrate for semiconductor device
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US Patent 7170165 Circuit board assembly with a brace surrounding a ball-grid array device
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US Patent 7170183 Wafer level stacked package
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US Patent 7176560 Semiconductor device having a chip—chip structure
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US Patent 7180170 Lead-free integrated circuit package structure
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US Patent 7180196 Semiconductor device mounting method, semiconductor device mounting structure, electro-optical device, electro-optical device manufacturing method and electronic device
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US Patent 7190060 Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same
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US Patent 7190080 Semiconductor chip assembly with embedded metal pillar
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US Patent 7193303 Supporting frame for surface-mount diode package
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US Patent 7196426 Multilayered substrate for semiconductor device
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US Patent 7196427 Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element
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US Patent 7199458 Stacked offset semiconductor package and method for fabricating
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US Patent 7199459 Semiconductor package without bonding wires and fabrication method thereof
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US Patent 7199469 Semiconductor device having stacked semiconductor chips sealed with a resin seal member
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US Patent 7205646 Electronic device and chip package
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US Patent 7205657 Complimentary lateral nitride transistors
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US Patent 7205668 Multi-layer printed circuit board wiring layout
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US Patent 7205673 Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing
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US Patent 7208825 Stacked semiconductor packages
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US Patent 7208831 Semiconductor device having multilayer wiring structure and method, wherein connecting portion and wiring layer are formed of same layer
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US Patent 7208833 Electronic circuit device having circuit board electrically connected to semiconductor element via metallic plate
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US Patent 7208843 Routing design to minimize electromigration damage to solder bumps
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US Patent 7215021 Electronic device
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US Patent 7217995 Apparatus for stacking electrical components using insulated and interconnecting via
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US Patent 7224046 Multilayer wiring board incorporating carbon fibers and glass fibers
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US Patent 7224047 Semiconductor device package with reduced leakage
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US Patent 7224050 Plastic materials including dendrimers or hyperbranched polymers for integrated circuit packaging
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US Patent 7224052 IC card with controller and memory chips
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US Patent 7224053 Semiconductor device responsive to different levels of input and output signals and signal processing system using the same
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US Patent 7224062 Chip package with embedded panel-shaped component
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US Patent 7224064 Semiconductor device having conductive interconnections and porous and nonporous insulating portions
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US Patent 7227198 Half-bridge package
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US Patent 7227240 Semiconductor device with wire bond inductor and method
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US Patent 7227246 Matching circuits on optoelectronic devices
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US Patent 7227249 Three-dimensional stacked semiconductor package with chips on opposite sides of lead
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US Patent 7227251 Semiconductor device and a memory system including a plurality of IC chips in a common package
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US Patent 7227252 Semiconductor component having stacked, encapsulated dice and method of fabrication
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US Patent 7230320 Electronic circuit device with reduced breaking and cracking
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US Patent 7230332 Chip package with embedded component
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US Patent 7230337 Semiconductor device including ladder-shaped siloxane hydride and method for manufacturing same
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US Patent 7230338 Semiconductor device that improves electrical connection reliability
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US Patent 7235871 Stacked microelectronic dies
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US Patent 7239002 Integrated circuit device
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US Patent 7239024 Semiconductor package with recess for die
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US Patent 7239028 Semiconductor device with signal line having decreased characteristic impedance
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US Patent 7242025 Radiation emitting semiconductor component having a nitride compound semiconductor body and a contact metallization layer on its surface
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US Patent 7242078 Surface mount multichip devices
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US Patent 7242085 Semiconductor device including a semiconductor chip mounted on a metal base
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US Patent 7242099 Chip package with multiple chips connected by bumps
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US Patent 7245022 Semiconductor module with improved interposer structure and method for forming the same
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US Patent 7247932 Chip package with capacitor
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US Patent 7247934 Multi-chip semiconductor package
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US Patent 7247939 Metal filled semiconductor features with improved structural stability
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US Patent 7247944 Connector assembly
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US Patent 7247951 Chip carrier with oxidation protection layer
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US Patent 7253504 Integrated circuit package and method
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US Patent 7253505 IC substrate with over voltage protection function
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US Patent 7253514 Self-supporting connecting element for a semiconductor chip
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US Patent 7253519 Chip packaging structure having redistribution layer with recess
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US Patent 7253520 CSP semiconductor device having signal and radiation bump groups
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US Patent 7256431 Insulating substrate and semiconductor device having a thermally sprayed circuit pattern
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US Patent 7256496 Semiconductor device having adhesion increasing film to prevent peeling
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US Patent 7256497 Semiconductor device with a barrier layer and a metal layer
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US Patent 7259451 Invertible microfeature device packages
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US Patent 7262498 Assembly with a ring and bonding pads formed of a same material on a substrate
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US Patent 7262500 Interconnection structure
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US Patent 7262510 Chip package structure
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US Patent 7265453 Semiconductor component having dummy segments with trapped corner air
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US Patent 7268438 Semiconductor element including a wet prevention film
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US Patent 7274105 Thermal conductive electronics substrate and assembly
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US Patent 7276787 Silicon chip carrier with conductive through-vias and method for fabricating same
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US Patent 7279787 Microelectronic complex having clustered conductive members
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US Patent 7282793 Multiple die stack apparatus employing T-shaped interposer elements
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US Patent 7282803 Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen
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US Patent 7285850 Support elements for semiconductor devices with peripherally located bond pads
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US Patent 7285862 Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film
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US Patent 7291904 Downsized package for electric wave device
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US Patent 7291923 Tapered signal lines
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US Patent 7291926 Multi-chip package structure
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US Patent 7294530 Method for encapsulating multiple integrated circuits
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US Patent 7294853 Substrate for mounting a semiconductor
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US Patent 7294904 Integrated circuit package with improved return loss
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US Patent 7294928 Components, methods and assemblies for stacked packages
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US Patent 7298046 Semiconductor package having non-ceramic based window frame
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US Patent 7301232 Integrated circuit package with carbon nanotube array heat conductor
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US Patent 7301241 Semiconductor device for preventing defective filling of interconnection and cracking of insulating film
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US Patent 7307293 Direct-connect integrated circuit signaling system for bypassing intra-substrate printed circuit signal paths
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US Patent 7312521 Semiconductor device with holding member
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US Patent 7312528 Semiconductor device having antenna connection electrodes
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US Patent 7321160 Multi-part lead frame
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US Patent 7323769 High performance chip scale leadframe package with thermal dissipating structure and annular element and method of manufacturing package
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US Patent 7323776 Elevated heat dissipating device
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US Patent 7327032 Semiconductor package accomplishing fan-out structure through wire bonding
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US Patent 7329947 Heat treatment jig for semiconductor substrate
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US Patent 7332756 Damascene gate structure with a resistive device
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US Patent 7332806 Thin, thermally enhanced molded package with leadframe having protruding region
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US Patent 7335972 Heterogeneously integrated microsystem-on-a-chip
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US Patent 7339260 Wiring board providing impedance matching
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US Patent 7339282 Topographically indexed support substrates
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US Patent 7342306 High performance reworkable heatsink and packaging structure with solder release layer
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US Patent 7342308 Component stacking for integrated circuit electronic package
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US Patent 7348664 Semiconductor apparatus having a cooling apparatus that compressively engages a semiconductor device
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US Patent 7352054 Semiconductor device having conducting portion of upper and lower conductive layers
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US Patent 7352059 Low loss interconnect structure for use in microelectronic circuits
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US Patent 7352060 Multilayer wiring substrate for providing a capacitor structure inside a multilayer wiring substrate
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US Patent 7352061 Flexible core for enhancement of package interconnect reliability
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US Patent 7355264 Integrated passive devices with high Q inductors
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US Patent 7355272 Semiconductor device with stacked semiconductor chips of the same type
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US Patent 7358599 Optical semiconductor device having a lead frame and electronic equipment using same
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US Patent 7358602 Semiconductor chip, and semiconductor wafer including a variable thickness insulating layer
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US Patent 7361991 Closed air gap interconnect structure
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US Patent 7368810 Invertible microfeature device packages
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US Patent 7372139 Semiconductor chip package
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US Patent 7372153 Integrated circuit package bond pad having plurality of conductive members
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US Patent 7382000 Semiconductor device
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US Patent 7385281 Semiconductor integrated circuit device
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US Patent 7388293 Interposer method of fabricating same, and semiconductor device using the same having two portions with different constructions
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US Patent 7397125 Semiconductor device with bonding pad support structure
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US Patent 7400032 Module assembly for stacked BGA packages
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US Patent 7400035 Semiconductor device having multilayer printed wiring board
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US Patent 7687917 Single damascene structure semiconductor device having silicon-diffused metal wiring layer
Edits on 4 Dec, 2021
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Golden AI
edited on 4 Dec, 2021
Edits on 30 Nov, 2021
Golden AI profile picture
Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7400032 Module assembly for stacked BGA packages
Golden AI profile picture
Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7400035 Semiconductor device having multilayer printed wiring board
Golden AI profile picture
Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7397125 Semiconductor device with bonding pad support structure
Edits on 30 Nov, 2021
Golden AI profile picture
Golden AI
edited on 30 Nov, 2021
Golden AI profile picture
Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7385281 Semiconductor integrated circuit device
Golden AI profile picture
Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7382000 Semiconductor device
Edits on 26 Nov, 2021
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7372153 Integrated circuit package bond pad having plurality of conductive members
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7372139 Semiconductor chip package
Edits on 26 Nov, 2021
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7368810 Invertible microfeature device packages
Edits on 25 Nov, 2021
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7361991 Closed air gap interconnect structure
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7358599 Optical semiconductor device having a lead frame and electronic equipment using same
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7355272 Semiconductor device with stacked semiconductor chips of the same type
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7355264 Integrated passive devices with high Q inductors
Golden AI profile picture
Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7352061 Flexible core for enhancement of package interconnect reliability
Golden AI profile picture
Golden AI
edited on 24 Nov, 2021
Golden AI profile picture
Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7352059 Low loss interconnect structure for use in microelectronic circuits

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