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J. H. Hur

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Edits on 14 Dec, 2021
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edited on 14 Dec, 2021
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Patent primary examiner of
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US Patent 7116589 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
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US Patent 7120083 Structure and method for transferring column address
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US Patent 7123509 Floating body cell memory and reading and writing circuit thereof
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US Patent 7139198 Efficient verification for coarse/fine programming of non-volatile memory
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US Patent 7139203 Voltage regulator and data path for a memory device
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US Patent 7142468 Control method of semiconductor memory device and semiconductor memory device
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US Patent 7142479 Addressing data within dynamic random access memory
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US Patent 7149114 Latch circuit and method for writing and reading volatile and non-volatile data to and from the latch
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US Patent 7149131 Semiconductor memory device and internal voltage generating method thereof
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US Patent 7164601 Multi-level nonvolatile semiconductor memory device utilizing a nonvolatile semiconductor memory device for storing binary data
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US Patent 7167389 Magnetic random access memory with a reference cell array and dummy cell arrays
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US Patent 7173847 Magnetic storage cell
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US Patent 7177178 magnetic memory layers thermal pulse transitions
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US Patent 7177197 Latched programming of memory and method
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US Patent 7184289 Parallel electrode memory
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US Patent 7184319 Method for erasing non-volatile memory cells and corresponding memory device
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US Patent 7187602 Reducing memory failures in integrated circuits
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US Patent 7196962 Packet addressing programmable dual port memory devices and related methods
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US Patent 7200035 Magneto-resistive memory cell structures with improved selectivity
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US Patent 7200047 High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devices
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US Patent 7203083 Longest match detection in a CAM
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US Patent 7203125 Word line driving circuit with a word line detection circuit
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US Patent 7209382 Magnetic random access memory
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US Patent 7221586 Memory utilizing oxide nanolaminates
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US Patent 7227801 Semiconductor memory device with reliable fuse circuit
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US Patent 7230868 Stable source-coupled sense amplifier
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US Patent 7233531 SRAM cell with horizontal merged devices
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US Patent 7236397 Redundancy circuit for NAND flash memory device
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US Patent 7245520 Random access memory including nanotube switching elements
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US Patent 7248523 Static random access memory (SRAM) with replica cells and a dummy cell
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US Patent 7254055 Initial firing method and phase change memory device for performing firing effectively
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US Patent 7254077 Circuit and method for high speed sensing
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US Patent 7263014 Semiconductor memory device having N-bit prefetch type and method of transferring data thereof
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US Patent 7266013 Magnetic memory layers thermal pulse transitions
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US Patent 7269061 Magnetic memory
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US Patent 7269068 Flash memory device and method of programming the same
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US Patent 7274605 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
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US Patent 7289379 Memory devices and methods of operation thereof using interdependent sense amplifier control
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US Patent 7292492 SRAM, semiconductor memory device, method for maintaining data in SRAM, and electronic device
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US Patent 7292498 Factored nanoscale multiplexer/demultiplexer circuit for interfacing nanowires with microscale and sub-microscale electronic devices
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US Patent 7301830 Semiconductor memory device and semiconductor device and semiconductor memory device control method
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US Patent 7304897 Method and system for reading data from a memory
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US Patent 7307874 Methods of operating magnetic random access memory devices including magnets adjacent magnetic tunnel junction structures
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US Patent 7315469 Control of set/reset pulse in response to peripheral temperature in PRAM device
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US Patent 7317638 Efficient verification for coarse/fine programming of non-volatile memory
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US Patent 7330368 Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections
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US Patent 7330374 Nonvolatile semiconductor memory device, such as an EEPROM or a flash memory, with reference cells
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US Patent 7333385 Semiconductor memory device having the operating voltage of the memory cell controlled
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US Patent 7336523 Memory device using nanotube cells
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US Patent 7336539 Method of operating flash memory cell
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US Patent 7336545 Semiconductor device having switch circuit to supply voltage
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US Patent 7339825 Nonvolatile semiconductor memory with write global bit lines and read global bit lines
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US Patent 7339827 Non-volatile semiconductor memory device and writing method thereof
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US Patent 7339849 Internal voltage supply circuit of a semiconductor memory device with a refresh mode
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US Patent 7342832 Bit line pre-settlement circuit and method for flash memory sensing scheme
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US Patent 7349246 Initial firing method and phase change memory device for performing firing effectively
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US Patent 7349289 Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM
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US Patent 7352601 USB flash memory device
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US Patent 7362605 Nanoelectromechanical memory cells and data storage devices
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US Patent 11182241 Grouping bits of a code word for memory device operations
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US Patent 11183228 Memory circuit device including a selection circuit unit shared by a write circuit unit and a read circut unit
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US Patent 7369456 DRAM memory with autoprecharge
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US Patent 7372748 Voltage regulator in a non-volatile memory device
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US Patent 7372757 Magnetic memory device with moving magnetic domain walls
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US Patent 7372759 Power supply control circuit and controlling method thereof
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US Patent 7379323 Memory with a refresh portion for rewriting data
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US Patent 7382674 Static random access memory (SRAM) with clamped source potential in standby mode
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US Patent 7394701 Circuit and method of driving a word line by changing the capacitance of a clamp capacitor to compensate for a fluctuation of a power supply voltage level
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US Patent 7397727 Write burst stop function in low power DDR sDRAM
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US Patent 7403413 Multiple port resistive memory cell
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US Patent 7408811 NAND-type flash memory on an SOI substrate with a carrier discharging operation
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US Patent 7411808 Method for reading ROM cell
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US Patent 7411853 Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits
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US Patent 7414872 Segmented search line circuit device for content addressable memory
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US Patent 7414900 Method and system for reading data from a memory
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US Patent 7417907 Systems and methods for resolving memory address collisions
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US Patent 7420837 Method for switching magnetic moment in magnetoresistive random access memory with low current
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US Patent 7426133 Complementary giant magneto-resistive memory with full-turn word line
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US Patent 7428181 Semiconductor device with self refresh test mode
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US Patent 7430137 Non-volatile memory cells in a field programmable gate array
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US Patent 7433237 Memory utilizing oxide nanolaminates
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US Patent 7433250 Sense amplifier circuit
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US Patent 7433252 Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device
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US Patent 7433261 Directed auto-refresh for a dynamic random access memory
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US Patent 7440314 Toggle-type magnetoresistive random access memory
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US Patent 7440336 Memory device having terminals for transferring multiple types of data
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US Patent 7443728 NAND flash memory device and method of programming same
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US Patent 7447062 Method and structure for increasing effective transistor width in memory arrays with dual bitlines
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US Patent 7450419 Semiconductor device and control method therefor
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US Patent 7457157 NAND flash memory devices and methods of LSB/MSB programming the same
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US Patent 7460385 Memory circuit arrangement with a cell array substrate and a logic circuit substrate and method for the production thereof
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US Patent 7466592 Semiconductor memory device
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US Patent 7466608 Data input/output circuit having data inversion determination function and semiconductor memory device having the same
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US Patent 7466609 Semiconductor memory device and semiconductor memory device control method
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US Patent 7466623 Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof
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US Patent 7471550 Magnetic memory
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US Patent 7474581 Memory synchronization method and refresh control circuit
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US Patent 7480173 Spin transfer MRAM device with novel magnetic free layer
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US Patent 7480178 NAND flash memory device having dummy memory cells and methods of operating same
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US Patent 7483332 SRAM cell using separate read and write circuitry
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US Patent 7489546 NAND architecture memory devices and operation
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US Patent 7492648 Reducing leakage current in memory device using bitline isolation
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US Patent 7492658 Apparatus and method for self-refreshing dynamic random access memory cells
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US Patent 7502262 NAND type flash memory array and method for operating the same
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US Patent 7502276 Method and apparatus for multi-word write in domino read SRAMs
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US Patent 7505308 Systems involving spin-transfer magnetic random access memory
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US Patent 7505311 Semiconductor memory device
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US Patent 7505334 Measurement method for reading multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition
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US Patent 7505353 Multi-port semiconductor memory device having variable access paths and method
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US Patent 7511988 Static noise-immune SRAM cells
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US Patent 7515459 Method of programming a memory cell array using successive pulses of increased duration
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US Patent 7515490 Sensing circuit for organic memory
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US Patent 11189354 Nonvolatile memory device with a monitoring cell in a cell string
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US Patent 7518911 Method and system for programming multi-state non-volatile memory devices
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US Patent 7518918 Method and apparatus for repairing embedded memory in an integrated circuit
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US Patent 7518928 Efficient verification for coarse/fine programming of non volatile memory
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US Patent 7518930 Method for generating and adjusting selected word line voltage
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US Patent 7518935 Synchronous RAM memory circuit
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US Patent 7525862 Methods involving resetting spin-torque magnetic random access memory with domain wall
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US Patent 7525868 Multiple-port SRAM device
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US Patent 7535776 Circuit for improved SRAM write around with reduced read access penalty
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US Patent 7539057 Erase and program method of flash memory device for increasing program speed of flash memory device
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US Patent 7551475 Data shifting through scan registers
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US Patent 7554850 Nonvolatile memory device with load-supplying wired-or structure and an associated driving method
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US Patent 7558145 Word line control for improving read and write margins
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US Patent 7561469 Programming method to reduce word line to word line breakdown for NAND flash
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US Patent 7567460 Method of programming flash memory device
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US Patent 7577020 System and method for reading multiple magnetic tunnel junctions with a single select transistor
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US Patent 7580282 Floating-gate non-volatile memory architecture for improved negative bias distribution
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US Patent 7580288 Multi-level voltage adjustment
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US Patent 7602656 Power supply control circuit and controlling method thereof
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US Patent 7609544 Programmable semiconductor memory device
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US Patent 7609553 NAND flash memory device with burst read latency function
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US Patent 7616490 Programming non-volatile memory with dual voltage select gate structure
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US Patent 7616514 Apparatus and method for generating an imprint-stabilized reference voltage for use in a ferroelectric memory device
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US Patent 7626885 Column path circuit
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US Patent 7639534 Device, system, and method of bit line selection of a flash memory
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US Patent 7649777 Nonvolatile semiconductor memory cell matrix with divided write/erase, a method for operating the same, monolithic integrated circuits and systems
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US Patent 7649783 Delayed activation of selected wordlines in memory
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US Patent 7652942 Sense amplifier, semiconductor memory device including the same, and data sensing method
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US Patent 7652948 Nonvolatile memory devices and programming methods using subsets of columns
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US Patent 7660156 NAND flash memory with a programming voltage held dynamically in a NAND chain channel region
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US Patent 7660159 Method and device for programming control information
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US Patent 7663944 Semiconductor memory device and memory system using same
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US Patent 7663945 Semiconductor memory with a delay circuit
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US Patent 7663948 Dynamic random access memory (DRAM) for suppressing a short-circuit current
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US Patent 7668008 1-transistor type DRAM cell, a DRAM device and manufacturing method therefore, driving circuit for DRAM, and driving method therefor
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US Patent 7672184 Semiconductor memory device with refresh signal generator and its driving method
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US Patent 7675790 Over driving pin function selection method and circuit
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US Patent 7679977 Semiconductor memory device and test method thereof
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US Patent 7692945 Reconfigurable input/output in hierarchical memory link
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US Patent 7692947 Nonvolatile ferroelectric memory and control device using the same
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US Patent 7692952 Nanoscale wire coding for stochastic assembly
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US Patent 7706183 Read mode for flash memory
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US Patent 7710763 SRAM cell using separate read and write circuitry
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US Patent 7710787 Method of erasing an EEPROM device
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US Patent 7710791 Input circuit of a non-volatile semiconductor memory device
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US Patent 7719891 Non-volatile memory device
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US Patent 7724565 Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices
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US Patent 7729177 Page buffer for nonvolatile memory device
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US Patent 7746700 NAND architecture memory devices and operation
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US Patent 7751235 Semiconductor memory device and write and read methods of the same
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US Patent 7751267 Half-select compliant memory cell precharge circuit
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US Patent 7755932 Spin torque magnetic memory and offset magnetic field correcting method thereof
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US Patent 7764530 Memory circuit arrangement and method for the production thereof
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US Patent 7773416 Single poly, multi-bit non-volatile memory device and methods for operating the same
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US Patent 7778086 Erase operation control sequencing apparatus, systems, and methods
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US Patent 7787279 Integrated circuit having a resistive memory
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US Patent 7791948 Channel carrier discharging in a NAND flash memory on an insulating substrate or layer
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US Patent 7796459 Memory voltage control circuit
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US Patent 7808810 Multilevel nonvolatile memory cell comprising a resistivity-switching oxide or nitride and an antifuse
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US Patent 7813165 Magnetic memory layers thermal pulse transitions
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US Patent 7817454 Variable resistance memory with lattice array using enclosing transistors
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US Patent 7821855 Multi-port memory device
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US Patent 7821860 Stable temperature adjustment for refresh control
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US Patent 7835206 Semiconductor memory device capable of relieving defective bits found after packaging
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US Patent 7843730 Non-volatile memory with reduced charge fluence
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US Patent 7848145 Three dimensional NAND memory
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US Patent 7855924 Data processing memory circuit having pull-down circuit with on/off configuration
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US Patent 7855932 Low power word line control circuits with boosted voltage output for semiconductor memory
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US Patent 7859914 Non-volatile memory device, non-volatile memory system and control method for the non-volatile memory device in which driving ability of a selector transistor is varied
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US Patent 7864563 Magnetic random access memory
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US Patent 7864626 Interface circuit, memory interface system, and data reception method
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US Patent 7869276 Nand type memory and programming method thereof
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US Patent 7881114 NAND flash memory device having dummy memory cells and methods of operating same
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US Patent 7885097 Non-volatile memory array with resistive sense element block erase and uni-directional write
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US Patent 7885123 Integrated circuit for memory card and memory card using the circuit
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US Patent 7889553 Single-poly non-volatile memory cell
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US Patent 7894236 Nonvolatile memory devices that utilize read/write merge circuits
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US Patent 7894238 Semiconductor memory device with stacked memory cell structure
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US Patent 7894265 Non-volatile memory device and operation method of the same
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US Patent 7898894 Static random access memory (SRAM) cells
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US Patent 7903465 Memory array of floating gate-based non-volatile memory cells
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US Patent 7907452 Non-volatile memory cell programming method
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US Patent 7911823 Method of programming a non-volatile memory device
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US Patent 7911826 Integrated circuits with clearable memory elements
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US Patent 7911850 Method of programming flash memory device
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US Patent 7911869 Fuse-type memory cells based on irreversible snapback device
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US Patent 7920406 Increasing effective transistor width in memory arrays with dual bitlines
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US Patent 7920438 Semiconductor memory device having the operating voltage of the memory cell controlled
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US Patent 7924619 Programming method to reduce word line to word line breakdown for NAND flash
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US Patent 7924634 Repeater of global input/output line
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US Patent 7929346 Memory data detecting apparatus and method for controlling reference voltage based on error in stored data
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US Patent 7933154 Non-volatile memory device for reducing layout area of global wordline decoder and operation method thereof
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US Patent 7936618 Memory circuit and method of sensing a memory element
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US Patent 7936623 Universal structure for memory cell characterization
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US Patent 7940563 Nonvolatile storage device and bias control method thereof
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US Patent 7940575 Memory device and method providing logic connections for data transfer
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US Patent 7940593 Method and apparatus for verification of a gate oxide fuse element
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US Patent 7944746 Room temperature drift suppression via soft program after erase
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US Patent 7948784 Semiconductor memory device having vertical transistors
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US Patent 7948819 Integrated circuit having a memory with process-voltage-temperature control
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US Patent 7957204 Flash memory programming power reduction
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US Patent 7969799 Multiple memory standard physical layer macro function
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US Patent 7978503 Static semiconductor memory with a dummy call and a write assist operation
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US Patent 7978532 Erase method of flash memory device
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US Patent 7978533 NAND flash memory with a programming voltage held dynamically in a NAND chain channel region
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US Patent 7983078 Data retention of last word line of non-volatile memory arrays
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US Patent 7983082 Apparatus and method of multi-bit programming
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US Patent 7990751 Drive method of nanogap switching element and storage apparatus equipped with nanogap switching element
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US Patent 7990771 Program method of flash memory device
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US Patent 8000138 Scaleable memory systems using third dimension memory
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US Patent 8004869 Memory circuit arrangement and method for the production thereof
Edits on 8 Dec, 2021
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edited on 8 Dec, 2021
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US Patent 8004869 Memory circuit arrangement and method for the production thereof
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edited on 8 Dec, 2021
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US Patent 8000138 Scaleable memory systems using third dimension memory
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edited on 8 Dec, 2021
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US Patent 7990771 Program method of flash memory device
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edited on 8 Dec, 2021
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US Patent 7983082 Apparatus and method of multi-bit programming
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edited on 8 Dec, 2021
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US Patent 7983078 Data retention of last word line of non-volatile memory arrays
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Golden AI
edited on 8 Dec, 2021
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US Patent 7978532 Erase method of flash memory device
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7978503 Static semiconductor memory with a dummy call and a write assist operation
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edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7969799 Multiple memory standard physical layer macro function
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edited on 7 Dec, 2021
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Patent primary examiner of
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US Patent 7957204 Flash memory programming power reduction
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edited on 7 Dec, 2021
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US Patent 7948819 Integrated circuit having a memory with process-voltage-temperature control
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Golden AI
edited on 7 Dec, 2021
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Infobox
Patent primary examiner of
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US Patent 7948784 Semiconductor memory device having vertical transistors
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Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
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US Patent 7944746 Room temperature drift suppression via soft program after erase
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edited on 7 Dec, 2021
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Patent primary examiner of
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US Patent 7940593 Method and apparatus for verification of a gate oxide fuse element
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Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
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US Patent 7940575 Memory device and method providing logic connections for data transfer
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edited on 7 Dec, 2021
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US Patent 7940563 Nonvolatile storage device and bias control method thereof
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US Patent 7936623 Universal structure for memory cell characterization
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US Patent 7936618 Memory circuit and method of sensing a memory element

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