US Patent 7483332 SRAM cell using separate read and write circuitry

The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes at least one write transistor. The circuitry also includes a read circuit coupled to the SRAM cell core that includes at least one read transistor having a gate signal in common with the gate signal of the write transistor. The read transistor and the write transistor share a common gate signal, and each have an electrical characteristic, for which the electrical characteristic of the read transistor differs from that of the write transistor.