US Patent 7430137 Non-volatile memory cells in a field programmable gate array

A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a source, a drain, and a gate, the drain of the first p-channel MOS transistor electrically coupled to the drain of the first floating gate transistor forming a first common node. A second p-channel MOS transistor has a source, a drain, and a gate, the first drain of the second p-channel MOS transistor electrically coupled to the drain of the second floating gate transistor forming a second common node, the gate of the second p-channel MOS transistor electrically coupled to the first common node, and the second common node electrically coupled to the gate of the first p-channel MOS transistor.