Patent attributes
A DRAM memory comprises a memory cell bank comprised of memory cells being activated by means of internal row and column access instructions, a command decoder generating, dependent on an external memory access instruction, at least one column access instruction within a first and at least one row access instruction within a second decoding time, and a clock signal delay circuit for delaying an external clock signal with the first decoding time for generating an internal column clock signal and for delaying the external clock signal with the second decoding time for generating an internal row clock signal. Each memory cell bank comprises an associated APC counter for delaying a column access instruction with autoprecharge. Each of the column access instructions are respectively delayed by an associated shift register being clocked by the internal column clock signal for generating the internal column access instructions. The APC counter is clocked by the internal row clock signal and delays each of the column access instructions in accordance with an associated programmable count for producing an internal autoprecharge instruction for the associated memory cell bank.
