Patent attributes
A merged structure SRAM cell is provided that includes a first transistor and a second transistor. The second transistor gate forms a load resistor for the first transistor and the first transistor gate forms a load resistor for the second transistor. Also provided is a method of reading a memory cell that comprises applying a potential difference (VDIFF) to a selected memory cell by providing a column line potential (VC) and a row line potential (VR). According to this method, VDIFF is increased by an increment less than a transistor threshold voltage (VT). It is then determined whether the increased VDIFF results in a current flow on the column line for the selected memory cell. Also provided is a method of writing a memory cell that comprises applying VDIFF and increasing VDIFF by an increment more than VT to set the selected memory cell to a one state.
