Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
August 17, 2010
Patent Application Number
11657949
Date Filed
January 25, 2007
Patent Primary Examiner
Patent abstract
Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
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