US Patent 7710763 SRAM cell using separate read and write circuitry

An SRAM device that includes an array of SRAM cells arranged in rows and columns. The SRAM device also includes a word line associated with at least one row, the word line operable to control access to cells in the row for both read and write. In addition, the SRAM device includes a write bit-line associated with at least one column operable to provide input to the cells in the column for write. Furthermore, the SRAM device includes a read bit-line associated with the column operable to receive output from cells in the column.