US Patent 8000138 Scaleable memory systems using third dimension memory

A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension memory arrays formed over the substrate. Each memory circuit can include an embedded controller for controlling data access to the memory arrays and optionally a control node that allows data access to be controlled by an external memory controller or by the embedded controller. The memory circuits can be chained together to increase memory capacity. The memory arrays can be two-terminal cross-point arrays that may be stacked upon one another.