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James C. Kerveros

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Edits on 15 Dec, 2021
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Golden AI
edited on 15 Dec, 2021
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Infobox
Patent primary examiner of
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US Patent 7096395 Efficient word recognizer for a logic analyzer
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US Patent 7103814 Testing logic and embedded memory in parallel
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US Patent 7107508 Manufacturing test for a fault tolerant magnetoresistive solid-state storage device
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US Patent 7114111 Method and apparatus for maximizing test coverage
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US Patent 7114119 Detecting and correcting errors in data
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US Patent 7117412 Flip-flop circuit for capturing input signals in priority order
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US Patent 7120838 Method and unit for deskewing signals
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US Patent 7124334 Test circuit and test method for communication system
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US Patent 7124339 Scan path circuit and semiconductor integrated circuit comprising the scan path circuit
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US Patent 7124343 Radio communication system
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US Patent 7131041 Semiconductor integrated circuit device and device for testing same
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US Patent 7131042 Semiconductor device and method for testing the same
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US Patent 7131046 System and method for testing circuitry using an externally generated signature
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US Patent 7134058 Memory circuit scan arrangement
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US Patent 11175984 Erasure coding techniques for flash memory
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US Patent 7137049 Method and apparatus for masking known fails during memory tests readouts
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US Patent 7137053 Bandwidth matching for scan architectures in an integrated circuit
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US Patent 7139954 Method and apparatus for testing a computing device with memory using test program code
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US Patent 7143327 Method and system for compressing repetitive data, in particular data used in memory device testing
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US Patent 7143330 Method and apparatus for transmitting acknowledgement signals
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US Patent 7146548 Fixing functional errors in integrated circuits
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US Patent 7149939 Method of testing the data exchange functionality of a memory
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US Patent 7152193 Embedded sequence checking
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US Patent 7162671 Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device
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US Patent 7162673 Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing
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US Patent 7165196 Method for testing serializers/de-serializers
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US Patent 7165203 Method for controlling data retransmission and control unit for implementing the method
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US Patent 7171595 Content addressable memory match line detection
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US Patent 7171596 Circuit and method for testing embedded DRAM circuits through direct access mode
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US Patent 7171600 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device
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US Patent 7174488 Echo canceler-based mechanism for performing and reporting fault diagnostic testing of repeatered telecommunication line
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US Patent 7178072 Methods and apparatus for storing memory test information
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US Patent 7178079 Reception data synchronizing apparatus and method, and recording medium with recorded reception data synchronizing program
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US Patent 7181664 Method on scan chain reordering for lowering VLSI power consumption
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US Patent 7181668 Method and system of decoding an encoded data block
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US Patent 7185244 Semiconductor integrated circuit and electronic system
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US Patent 7188290 Data alignment for telecommunications networks
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US Patent 7191372 Integrated data download
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US Patent 7191373 Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
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US Patent 7194668 Event based test method for debugging timing related failures in integrated circuits
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US Patent 7194669 Method and circuit for at-speed testing of scan circuits
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US Patent 7197680 Communication interface for diagnostic circuits of an integrated circuit
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US Patent 7197684 Single-ended transmission for direct access test mode within a differential input and output circuit
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US Patent 7199592 Method and apparatus for applying microwaves to measure the moisture content of material
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US Patent 7203882 Clustering-based approach for coverage-directed test generation
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US Patent 7203892 Row-diagonal parity technique for enabling efficient recovery from double failures in a storage array
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US Patent 7206981 Compliance testing through test equipment
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US Patent 7206988 Error-correction memory architecture for testing production errors
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US Patent 7206989 Integrated circuit having multiple modes of operation
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US Patent 7213188 Accessing test modes using command sequences
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US Patent 7216274 Flexible scan architecture
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US Patent 7219274 Memory module and method of testing the same
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US Patent 7219286 Built off self test (BOST) in the kerf
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US Patent 7222275 Test apparatus and writing control circuit
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US Patent 7222276 Scan test circuit including a control test mode
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US Patent 7222277 Test output compaction using response shaper
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US Patent 7222280 Diagnostic process for automated test equipment
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US Patent 7225370 Eye width characterization mechanism
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US Patent 7225375 Method and apparatus for detecting array degradation and logic degradation
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US Patent 7225384 Method for controlling turbo decoding time in a high-speed packet data communication system
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US Patent 7228464 PICA system timing measurement and calibration
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US Patent 7231570 Method and apparatus for multi-level scan compression
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US Patent 7234089 Tristate buses
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US Patent 7234093 Resource management during system verification
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US Patent 7234094 Automaton synchronization during system verification
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US Patent 7237165 Method for testing embedded DRAM arrays
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US Patent 7240265 Apparatus for use in detecting circuit faults during boundary scan testing
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US Patent 7243272 Testing of integrated circuit receivers
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US Patent 7243274 Semiconductor device
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US Patent 7243278 Integrated circuit tester with software-scaleable channels
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US Patent 7246291 Method for localization and generation of short critical sequence
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US Patent 7249300 Integrated circuit device including a scan test circuit and methods of testing the same
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US Patent 7251758 Semiconductor device testing apparatus, system, and method for testing the contacting with semiconductor devices positioned one upon the other
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US Patent 7254756 Data compression read mode for memory testing
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US Patent 7254763 Built-in self test for memory arrays using error correction coding
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US Patent 7256589 Capacitive sensor system with improved capacitance measuring sensitivity
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US Patent 7256611 Cross-bar matrix with LCD functionality
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US Patent 7257753 Semiconductor testing apparatus
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US Patent 7257756 Digital frequency synthesis clocked circuits
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US Patent 7260758 Method and system for performing built-in self-test routines using an accumulator to store fault information
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US Patent 7263643 Test apparatus and testing method
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US Patent 7263644 Data transmitting/receiving system and method thereof
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US Patent 7263648 Apparatus and method for accommodating loss of signal
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US Patent 7266740 Methods of testing a digital frequency synthesizer in a programmable logic device using a reduced set of multiplier and divider values
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US Patent 7266741 Generation of test vectors for testing electronic circuits taking into account of defect probability
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US Patent 7269782 Orthogonal frequency division multiplexing/modulation communication system for improving ability of data transmission and method thereof
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US Patent 7272760 Curve tracing device and method
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US Patent 7272765 Test apparatus and test method for testing plurality of devices in parallel
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US Patent 7272774 Extender card for testing error-correction-code (ECC) storage area on memory modules
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US Patent 7275191 Coverage decoder circuit for performance counter
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US Patent 7275192 Method and system for on demand selective rerouting of logical circuit data in a data network
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US Patent 7275194 Clock duty cycle based access timer combined with standard stage clocked output register
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US Patent 7278073 Diagnostic data capture within an integrated circuit
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US Patent 7281185 Method and apparatus for maximizing and managing test coverage
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US Patent 7284175 Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
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US Patent 7284178 Method and apparatus for testing a device in an electronic component
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US Patent 7285962 Method and apparatus for evaluating susceptibility to common mode noise in a computer system
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US Patent 7290183 Method of testing semiconductor apparatus
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US Patent 7290186 Method and apparatus for a command based bist for testing memories
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US Patent 7290188 Method and apparatus for capturing the internal state of a processor for second and higher order speepaths
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US Patent 7290193 System verification using one or more automata
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US Patent 7290194 System for performing automatic test pin assignment for a programmable device
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US Patent 7293209 Split L2 latch with glitch free programmable delay
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US Patent 7296198 Method for testing semiconductor memory modules
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US Patent 7296201 Method to locate logic errors and defects in digital circuits
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US Patent 7299394 Method and apparatus for determining optimum initial value for test pattern generator
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US Patent 7299396 Methods and apparatus for error detection and correction of an electronic shelf label system communication error
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US Patent 7302623 Algorithm pattern generator for testing a memory device and memory tester using the same
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US Patent 7305601 Method and test apparatus for testing integrated circuits using both valid and invalid test data
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US Patent 7305602 Merged MISR and output register without performance impact for circuits under test
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US Patent 7305604 Determining edge relationship between clock signals
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US Patent 7308621 Testing of ECC memories
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US Patent 7308623 Integrated circuit and method for testing memory on the integrated circuit
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US Patent 7308628 Input switching arrangement for a semiconductor circuit and test method for unidirectional input drivers in semiconductor circuits
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US Patent 7308631 Wrapper serial scan chain functional segmentation
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US Patent 7308633 Master controller architecture
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US Patent 7310754 Integrated test circuit, a test circuit, and a test method for performing transmission and reception processing to and from a first and a second macro block at a first frequency
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US Patent 7313745 Decoder for pin-based scan test
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US Patent 7315969 Memory module with a test device
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US Patent 7315971 Systems and methods for improved memory scan testability
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US Patent 7319346 Circuit and method for trimming integrated circuits
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US Patent 7320097 Serial to parallel conversion circuit having a shift clock frequency lower than a data transfer frequency
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US Patent 7322001 Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance
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US Patent 7325177 Test circuit and method for multilevel cell flash memory
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US Patent 7325179 Storage system comprising logical circuit configured in accordance with information in memory on PLD
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US Patent 7328384 Method and apparatus using device defects as an identifier
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US Patent 7328386 Methods for using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits
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US Patent 7333360 Apparatus for pulse testing a MRAM device and method therefore
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US Patent 7334168 Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit
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US Patent 7334173 Method and system for protecting processors from unauthorized debug access
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US Patent 7334174 Semiconductor integrated circuit device and error detecting method therefor
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US Patent 7337380 Eye width characterization mechanism
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US Patent 7343558 Configurable automatic-test-equipment system
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US Patent 7346816 Method and system for testing memory using hash algorithm
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US Patent 7346820 Testing of data retention latches in circuit devices
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US Patent 7350120 Buffered memory module and method for testing same
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US Patent 7350121 Programmable embedded logic analyzer in an integrated circuit
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US Patent 7350137 Method and circuit for error correction in CAM cells
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US Patent 7353440 Multicore processor test method
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US Patent 7353441 Flip flop circuit and apparatus using a flip flop circuit
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US Patent 7353443 Providing high availability in a PCI-Express link in the presence of lane faults
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US Patent 7356747 Decision selection and associated learning for computing all solutions in automatic test pattern generation (ATPG) and satisfiability
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US Patent 7360135 Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance
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US Patent 7360139 Semiconductor component, arrangement and method for characterizing a tester for semiconductor components
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US Patent 7363551 Systems and methods for measuring signal propagation delay between circuits
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US Patent 11182243 Memory system with adaptive information propagation and method of operating such memory
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US Patent 11184027 Encoding method and encoder
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US Patent 7366967 Methods of testing semiconductor memory devices in a variable CAS latency environment and related semiconductor test devices
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US Patent 7370245 Cross-correlation of delay line characteristics
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US Patent 7370251 Method and circuit for collecting memory failure information
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US Patent 7373565 Start/stop circuit for performance counter
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US Patent 7373566 Semiconductor device for accurate measurement of time parameters in operation
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US Patent 7373576 Apparatus, method, and signal-bearing medium embodying a program for verifying logic circuit design
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US Patent 7373583 ECC flag for testing on-chip error correction circuit
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US Patent 7380185 Reduced pin count scan chain implementation
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US Patent 7383482 Abnormality detecting device and method of detecting an abnormality in a head of hard disk
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US Patent 7386774 Memory unit with controller managing memory access through JTAG and CPU interfaces
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US Patent 7386778 Methods for distributing programs for generating test data
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US Patent 7389450 Bit error rate measurement
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US Patent 7389460 Runtime-competitive fault handling for reconfigurable logic devices
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US Patent 7389461 Data capture in automatic test equipment
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US Patent 7395472 Method and a unit for programming a memory
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US Patent 7398442 Electronic circuit with asynchronously operating components
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US Patent 7398443 Automatic fault-testing of logic blocks using internal at-speed logic-BIST
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US Patent 7398444 Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods
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US Patent 7401270 Repair of semiconductor memory device via external command
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US Patent 7401279 Scan path circuit and semiconductor integrated circuit comprising the scan path circuit
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US Patent 7404116 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
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US Patent 7404118 Memory error analysis for determining potentially faulty memory components
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US Patent 7404121 Method and machine-readable media for inferring relationships between test results
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US Patent 7406645 Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus
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US Patent 7409608 Pseudo-random wait-state and pseudo-random latency components
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US Patent 7409625 Row-diagonal parity technique for enabling efficient recovery from double failures in a storage array
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US Patent 7412633 Communication interface for diagnostic circuits of an integrated circuit
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US Patent 7412636 Scan string segmentation for digital test compression
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US Patent 7412637 Method and apparatus for broadcasting test patterns in a scan based integrated circuit
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US Patent 7412639 System and method for testing circuitry on a wafer
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US Patent 7415643 Coverage circuit for performance counter
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US Patent 7415645 Method and apparatus for soft-error immune and self-correcting latches
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US Patent 7415647 Test mode for pin-limited devices
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US Patent 7418637 Methods and apparatus for testing integrated circuits
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US Patent 7418638 Semiconductor memory device and method for testing memory cells using several different test data patterns
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US Patent 7418641 Self-resetting, self-correcting latches
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US Patent 7421634 Sequential scan based techniques to test interface between modules designed to operate at different frequencies
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US Patent 7421636 Semiconductor memory device having a test control circuit
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US Patent 7424658 Method and apparatus for testing integrated circuits
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US Patent 7426669 Circuit arrangement and method for driving electronic chips
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US Patent 7430698 Method and system for an on-chip AC self-test controller
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US Patent 7434123 Single event functional interrupt detection system
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US Patent 7434125 Integrated circuit, test system and method for reading out an error datum from the integrated circuit
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US Patent 7436222 Circuit and method for trimming integrated circuits
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US Patent 7437631 Soft errors handling in EEPROM devices
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US Patent 7437637 Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing
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US Patent 7437639 Response bits as stimulus in subdivided scan path delay test
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US Patent 7437646 Test pattern generating method and apparatus and storing medium for storing test pattern generating program
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US Patent 7437652 Correcting multiple block data loss in a storage array using a combination of a single diagonal parity group and multiple row parity groups
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US Patent 7444562 Trie-type memory device with a compression mechanism
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US Patent 7444564 Automatic bit fail mapping for embedded memories with clock multipliers
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US Patent 7447969 Data transmitting/receiving system and method thereof
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US Patent 7451365 System and method for identifying nodes in a wireless network
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US Patent 7451367 Accessing sequential data in microcontrollers
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US Patent 7454671 Memory device testing system and method having real time redundancy repair analysis
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US Patent 7457992 Delay fault test circuitry and related method
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US Patent 7457993 Error free dynamic rate change in a digital subscriber line DSL with constant delay
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US Patent 7458001 Sequential pattern extracting apparatus
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US Patent 7461305 System and method for detecting and preventing race condition in circuits
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US Patent 7461307 System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop
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US Patent 7461315 Method and system for improving quality of a circuit through non-functional test pattern identification
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US Patent 7467343 Apparatus and method for performing a multi-value polling operation in a JTAG data stream
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US Patent 7467345 Fast H-ARQ acknowledgement generation method using a stopping rule for turbo decoding
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US Patent 7469369 Low power content-addressable-memory device
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US Patent 7469372 Scan sequenced power-on initialization
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US Patent 7475312 Integrated circuit (IC) with on-board characterization unit
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US Patent 7475318 Method for testing the sensitive input range of Byzantine filters
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US Patent 7478292 Structure and method for detecting errors in a multilevel memory device with improved programming granularity
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US Patent 7478297 Merged MISR and output register without performance impact for circuits under test
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US Patent 7478305 Method and apparatus for interactive generation of device response templates and analysis
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US Patent 7478308 Error-correction memory architecture for testing production
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US Patent 7480838 Method, system and apparatus for detecting and recovering from timing errors
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US Patent 7480841 Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit
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US Patent 7480844 Method for eliminating hold error in scan chain
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US Patent 7484138 Method and system for improving reliability of memory device
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US Patent 7484149 Negative edge flip-flops for muxscan and edge clock compatible LSSD
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US Patent 7484152 Securing the test mode of an integrated circuit
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US Patent 7484157 Data transmitting/receiving system and method thereof
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US Patent 7487413 Memory module testing apparatus and method of testing memory modules
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US Patent 7487420 System and method for performing logic failure diagnosis using multiple input signature register output streams
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US Patent 7490274 Method and apparatus for masking known fails during memory tests readouts
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US Patent 7490280 Microcontroller for logic built-in self test (LBIST)
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US Patent 7492683 Information recording method, information recording system, drive control unit, and semiconductor integrated circuit for recording information on a recording medium having a volume space
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US Patent 7493532 Methods and structure for optimizing SAS domain link quality and performance
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US Patent 7493541 Method and system for performing built-in-self-test routines using an accumulator to store fault information
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US Patent 7496816 Isolating the location of defects in scan chains
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US Patent 7500155 Average time extraction circuit for eliminating clock skew
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US Patent 7502980 Signal generator, test apparatus, and circuit device
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US Patent 7509542 System and method for testing the upstream channel of a cable network
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US Patent 7512858 Method and system for per-pin clock synthesis of an electronic device under test
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US Patent 7516375 Methods and systems for repairing an integrated circuit device
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US Patent 7516380 BIST to provide jitter data and associated methods of operation
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US Patent 7516382 On-chip data transmission control apparatus and method
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US Patent 7516385 Test semiconductor device in full frequency with half frequency tester
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US Patent 11187749 Test equipment for over the air tests as well as method for testing a device under test
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US Patent 7519891 IO self test method and apparatus for memory
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US Patent 7523363 Method and tester for determining the error rate of a mobile radio device with variable block allocation
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US Patent 7526688 Parallel bit testing device and method
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US Patent 7526689 Testing address lines of a memory controller
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US Patent 7526697 Memory test circuit and method
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US Patent 7526698 Error detection and correction in semiconductor structures
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US Patent 7529987 Integrity control for data stored in a non-volatile memory
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US Patent 7529992 Configurable integrated circuit with error correcting circuitry
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US Patent 7529993 Method of selectively programming integrated circuits to compensate for process variations and/or mask revisions
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US Patent 7529995 Second state machine active in first state machine SHIFT-DR state
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US Patent 7529999 Integrated circuit arrangement and method
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US Patent 7536611 Hard BISR scheme allowing field repair and usage of reliability controller
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US Patent 7536618 Wide frequency range signal generator and method, and integrated circuit test system using same
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US Patent 7539909 Distributed memory initialization and test methods and apparatus
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US Patent 7539916 BIST to provide phase interpolator data and associated methods of operation
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US Patent 7543206 Method for testing semiconductor integrated circuit and method for verifying design rules
‌
US Patent 7546494 Skew-correcting apparatus using dual loopback
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US Patent 7546507 Method and apparatus for debugging semiconductor devices
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US Patent 7549094 Method for receiving data by a universal asynchronous receiver transmitter
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US Patent 7549100 Dynamic verification traversal strategies
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US Patent 7555688 Method for implementing test generation for systematic scan reconfiguration in an integrated circuit
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US Patent 7558991 Device and method for measuring jitter
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US Patent 7562266 Method and device for verifying timing in a semiconductor integrated circuit
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US Patent 7562273 Register file cell with soft error detection and circuits and methods using the cell
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US Patent 7565582 Circuit for testing the AC timing of an external input/output terminal of a semiconductor integrated circuit
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US Patent 7565583 Multilink receiver for multiple cordless applications
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US Patent 7565584 Setting transmission length based on estimated error rate
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US Patent 7565589 Semiconductor integrated circuit having a BIST circuit
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US Patent 7565591 Testing of circuits with multiple clock domains
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US Patent 7568136 Reconfigurable system and method with corruption detection and recovery
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US Patent 7568137 Method and apparatus for a clock and data recovery circuit
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US Patent 7574632 Strobe technique for time stamping a digital signal
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US Patent 7574639 Method and apparatus for entering special mode in integrated circuit
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US Patent 7581148 System, method and apparatus for completing the generation of test records after an abort event
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US Patent 7587640 Method and apparatus for monitoring and compensating for skew on a high speed parallel bus
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US Patent 7587643 System and method of integrated circuit testing
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US Patent 7590906 Scan flip-flop circuit and semiconductor integrated circuit device
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US Patent 7590907 Method and apparatus for soft-error immune and self-correcting latches
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US Patent 7594157 Memory system with backup circuit and programming method
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US Patent 7596730 Test method, test system and assist board
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US Patent 7596734 On-Chip AC self-test controller
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US Patent 7596735 Pad unit having a test logic circuit and method of driving a system including the same
‌
US Patent 7596736 Iterative process for identifying systematics in data
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US Patent 7600166 Method and system for providing trusted access to a JTAG scan interface in a microprocessor
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US Patent 7603602 Built-in self test circuit for analog-to-digital converter and phase lock loop and the testing methods thereof
‌
US Patent 7603605 Performance control of an integrated circuit
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US Patent 7607060 System and method for performing high speed memory diagnostics via built-in-self-test
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US Patent 7613962 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
‌
US Patent 7613984 System and method for symmetric triple parity for failing storage devices
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US Patent 7620865 Scan string segmentation for digital test compression
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US Patent 7620866 Test access architecture and method of testing a module in an electronic circuit
‌
US Patent 7620869 Semiconductor integrated circuit and BIST circuit design method
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US Patent 7624314 Echo canceler-based mechanism for performing and reporting fault diagnostic testing of repeatered telecommunication line
‌
US Patent 7624316 Apparatus and method for testing removable flash memory devices
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US Patent 7624320 Apparatus for testing system-on-chip
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US Patent 7627794 Apparatus and method for discrete test access control of multiple cores
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US Patent 7631230 Method and apparatus for testing a transmission path
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US Patent 7631238 Method of testing a multichip
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US Patent 7634698 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
‌
US Patent 7634701 Method and system for protecting processors from unauthorized debug access
‌
US Patent 7636877 Test apparatus having a pattern memory and test method for testing a device under test
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US Patent 7640467 Semiconductor memory with a circuit for testing the same
‌
US Patent 7640468 Method and apparatus for an embedded time domain reflectometry test
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US Patent 7640476 Method and system for automated path delay test vector generation from functional tests
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US Patent 7640481 Integrated circuit having multiple modes of operation
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US Patent 7644325 Semiconductor integrated circuit device and method of testing the same
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US Patent 7644326 Testing system and testing system control method
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US Patent 7644328 Sharing routing of a test signal with an alternative power supply to combinatorial logic for low power design
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US Patent 7644329 Integrated circuit testing method and related circuit thereof
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US Patent 7650552 Apparatus and method for detecting and recovering errors caused by electrostatic discharge
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US Patent 7653846 Memory cell bit valve loss detection and restoration
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US Patent 7653854 Semiconductor integrated circuit having a (BIST) built-in self test circuit for fault diagnosing operation of a memory
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US Patent 7653856 Method and apparatus for transmitting acknowledgement signals
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US Patent 7657800 Semiconductor memory device and method of performing a memory operation
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US Patent 7657802 Data compression read mode for memory testing
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US Patent 7657805 Integrated circuit with blocking pin to coordinate entry into test mode
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US Patent 7661041 Test circuit and method for multilevel cell flash memory
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US Patent 7661042 Low-power content-addressable-memory device
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US Patent 7661048 Apparatus and method for embedded boundary scan testing
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US Patent 7661053 Methods and apparatus for patternizing device responses
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US Patent 7665001 Progressive random access scan circuitry
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US Patent 7669091 Apparatus and method for defect replacement
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US Patent 7669097 Configurable IC with error detection and correction circuitry
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US Patent 7669098 Method and apparatus for limiting power dissipation in test
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US Patent 7669101 Methods for distributing programs for generating test data
‌
US Patent 7673202 Single event upset test circuit and methodology
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US Patent 7673204 Method using non-linear compression to generate a set of test vectors for use in scan testing an integrated circuit
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US Patent 7673209 Test pattern generating circuit and semiconductor memory device having the same
‌
US Patent 7676708 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
‌
US Patent 7681095 Methods and apparatus for testing integrated circuits
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US Patent 7685481 Bitmap cluster analysis of defects in integrated circuits
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US Patent 7689878 System and method for testing defects in an electronic circuit
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US Patent 7694195 System and method for using a memory mapping function to map memory defects
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US Patent 7694203 On-chip samplers for asynchronously triggered events
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US Patent 7698610 Techniques for detecting open integrated circuit pins
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US Patent 7707468 System and method for electronic testing of multiple memory devices
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US Patent 7712000 ATE architecture and method for DFT oriented testing
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US Patent 7721162 System for testing the upstream channel of a cable network
‌
US Patent 7725788 Method and apparatus for secure scan testing
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US Patent 7730367 Method and system for testing devices using loop-back pseudo random data
‌
US Patent 7730369 Method for performing memory diagnostics using a programmable diagnostic memory module
‌
US Patent 7730376 Providing high availability in a PCI-Express™ link in the presence of lane faults
‌
US Patent 7730383 Structure and method for detecting errors in a multilevel memory device with improved programming granularity
‌
US Patent 7734968 Mechanism to provide test access to third-party macro circuits embedded in an ASIC (application-specific integrated circuit)
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US Patent 7734970 Self-resetting, self-correcting latches
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US Patent 7734974 Serial scan chain control within an integrated circuit
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US Patent 7739558 Method and apparatus for rectifying errors in the presence of known trapping sets in iterative decoders and expedited bit error rate testing
‌
US Patent 7739567 Utilizing serializer-deserializer transmit and receive pads for parallel scan test data
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US Patent 7739571 Semiconductor integrated circuit and system LSI having a test expected value programming circuit
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US Patent 7747912 Semiconductor memory device capable of arbitrarily setting the number of memory cells to be tested and related test method
‌
US Patent 7752511 Devices, systems, and methods regarding a PLC system fault
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US Patent 7757133 Built-in self-test hardware and method for generating memory tests with arbitrary address sequences
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US Patent 7757134 Test apparatus for testing a memory and electronic device housing a circuit
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US Patent 7757135 Method and apparatus for storing and distributing memory repair information
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US Patent 7757136 Testing system, testing system control method, and test apparatus
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US Patent 7757139 Boundary scan method, system and device
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US Patent 7757143 Semiconductor device including concealable test terminals
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US Patent 7757144 System and method for testing integrated circuit modules comprising a plurality of integrated circuit devices
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US Patent 7761756 Circuit configuration with serial test interface or serial test operating-mode procedure
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US Patent 7761765 Automated root cause identification of logic controller failure
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US Patent 7765444 Failure diagnosis for logic circuits
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US Patent 7765446 Method for testing semiconductor integrated circuit and method for verifying design rules
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US Patent 7765448 Clock signal distributing circuit, information processing device and clock signal distributing method
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US Patent 7770079 Error scanning in flash memory
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US Patent 7774668 System and method for detecting non-reproducible pseudo-random test cases
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US Patent 7779312 Built-in redundancy analyzer and method for redundancy analysis
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US Patent 7779319 Input-output device testing including delay tests
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US Patent 7783942 Integrated circuit device with built-in self test (BIST) circuit
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US Patent 7783947 Controller applying stimulus data while continuously receiving serial stimulus data
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US Patent 7788549 Apparatus and method for defect replacement
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US Patent 7788558 Semiconductor integrated circuit and control method thereof
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US Patent 7793175 Automated scan testing of DDR SDRAM
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US Patent 7793180 Scan architecture for full custom blocks
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US Patent 7797594 Built-in self-test of 3-dimensional semiconductor memory arrays
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US Patent 7802156 Identification circuit with repeatable output code
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US Patent 7805643 Non-volatile semiconductor memory device
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US Patent 7805645 Data processing apparatus and method for testing stability of memory cells in a memory device
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US Patent 7809999 Ternary search process
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US Patent 7810001 Parallel test system
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US Patent 7810002 Providing trusted access to a JTAG scan interface in a microprocessor
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US Patent 7814379 Memory module packaging test system
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US Patent 7818640 Test system having a master/slave JTAG controller
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US Patent 7823039 Data transmitting/receiving system and method thereof
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US Patent 7831872 Test circuit and method for multilevel cell flash memory
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US Patent 7831886 Fast H-ARQ acknowledgement generation method using a stopping rule for turbo decoding
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US Patent 7836361 Apparatus and method for deciding adaptive target packet error rate in wireless communication system
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US Patent 7840865 Built-in self-test of integrated circuits using selectable weighting of test patterns
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US Patent 7844875 Programmable test clock generation responsive to clock signal characterization
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US Patent 7849385 Systems and methods for media defect detection utilizing correlated DFIR and LLR data
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US Patent 7853836 Semiconductor integrated circuit
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US Patent 7853847 Methods and apparatuses for external voltage test of input-output circuits
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US Patent 7856581 Methods and apparatuses for external test methodology and initialization of input-output circuits
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US Patent 7865788 Dynamic mask memory for serial scan testing
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US Patent 7869293 Memory sense scan circuit and test interface
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US Patent 7870454 Structure for system for and method of performing high speed memory diagnostics via built-in-self-test
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US Patent 7873884 Wireless embedded test signal generation
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US Patent 7882407 Adapting word line pulse widths in memory systems
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US Patent 7890824 Asynchronous communication apparatus using JTAG test data registers
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US Patent 7895489 Matrix system and method for debugging scan structure
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US Patent 7904767 Semiconductor memory testing device and method of testing semiconductor using the same
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US Patent 7904769 Debugging system and method including an emulator for debugging a target device
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US Patent 7904771 Self-diagnostic circuit and self-diagnostic method for detecting errors
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US Patent 7904775 Microprocessor comprising signature means for detecting an attack by error injection
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US Patent 7908534 Diagnosable general purpose test registers scan chain design
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US Patent 7913134 Test circuit capable of sequentially performing boundary scan test and test method thereof
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US Patent 7917818 Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit
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US Patent 7921341 System and method for reproducing memory error
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US Patent 7921343 Testing system, testing system control method, and test apparatus
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US Patent 7925939 Pre-code device, and pre-code system and pre-coding method thererof
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US Patent 7925947 X-canceling multiple-input signature register (MISR) for compacting output responses with unknowns
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US Patent 7930607 Circuit for boosting encoding capabilities of test stimulus decompressors
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US Patent 7930608 Circuit for controlling voltage fluctuation in integrated circuit
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US Patent 7934135 Providing pseudo-randomized static values during LBIST transition tests
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US Patent 7939892 Test circuit and method for multilevel cell flash memory
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US Patent 7941711 Determining bit error rate using single data burst
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US Patent 7945825 Recovery while programming non-volatile memory (NVM)
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US Patent 7949916 Scan chain circuitry for delay fault testing of logic circuits
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US Patent 7954023 Semiconductor integrated circuit including power domains
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US Patent 7954025 Scan architecture for full custom blocks
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US Patent 7958422 Method and apparatus for generating self-verifying device scenario code
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US Patent 7962810 Recording medium structure capable of displaying defect rate
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US Patent 7962816 I/O switches and serializer for each parallel scan register
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US Patent 7962832 Method for detecting memory error
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US Patent 7971107 Calculation apparatus, calculation method, program, recording medium, test system and electronic device
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US Patent 7971109 Method for improving the integrity of communication means
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US Patent 7971111 Automated scan testing of DDR SDRAM
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US Patent 7971112 Memory diagnosis method
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US Patent 7979763 Fully X-tolerant, very high scan compression scan test systems and techniques
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US Patent 7979764 Distributed test compression for integrated circuits
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US Patent 7979779 System and method for symmetric triple parity for failing storage devices
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US Patent 7984358 Error-correction memory architecture for testing production errors
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US Patent 7996737 Fingerprinted circuits and methods of making and identifying the same
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US Patent 7996738 Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip
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US Patent 8006146 Test apparatus and test method for testing a plurality of devices under test
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US Patent 8006147 Error detection in precharged logic
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US Patent 8010855 Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit
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US Patent 8006147 Error detection in precharged logic
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US Patent 8006146 Test apparatus and test method for testing a plurality of devices under test
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US Patent 7996737 Fingerprinted circuits and methods of making and identifying the same
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US Patent 7984358 Error-correction memory architecture for testing production errors
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US Patent 7979779 System and method for symmetric triple parity for failing storage devices
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US Patent 7979764 Distributed test compression for integrated circuits
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US Patent 7979763 Fully X-tolerant, very high scan compression scan test systems and techniques
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US Patent 7971112 Memory diagnosis method
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US Patent 7971111 Automated scan testing of DDR SDRAM
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US Patent 7971109 Method for improving the integrity of communication means
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US Patent 7962832 Method for detecting memory error
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US Patent 7962816 I/O switches and serializer for each parallel scan register
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US Patent 7962810 Recording medium structure capable of displaying defect rate
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US Patent 7958422 Method and apparatus for generating self-verifying device scenario code
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US Patent 7954023 Semiconductor integrated circuit including power domains
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US Patent 7954025 Scan architecture for full custom blocks

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