Patent attributes
To test memories operating with different operational clocks and deal with a delay involved in testing a memory at a physically remote location. A memory test circuit of the present invention tests a processor core memory and a function-specific core memory with a processor core, and includes a clock selector receiving operational clocks for the processor core and for the function-specific core to select one of the two to be applied to the processor core, and a control unit supplying to the processor core, the operation clock for the processor core when testing the processor core memory, and the operational clock for the function-specific core when testing the function-specific core memory, by use of the selector. With this setting, it is possible to test a memory running at different operational clock and used by the function-specific core.
