Patent attributes
A flip flop circuit includes a first latch circuit which latches an input data at a leading edge of a clock signal, a second latch circuit which latches the input data at a trailing edge of the clock signal, and a selector which, during a period from the leading edge to the trailing edge of the clock signal, selects an output data from the first latch circuit, and during a period of the trailing edge to a next leading edge of the clock signal, selects an output data from the second latch circuit, in which one of the first latch circuit and the second latch circuit functions as a master latch circuit for receiving a scan data during a scan mode, and the other of the first latch circuit and the second latch circuit functions as a slave latch circuit for latching data outputted from the master latch circuit.
