US Patent 7222276 Scan test circuit including a control test mode

A scan test circuit (100) including a path for capturing a control signal during a test mode is disclosed. Scan test circuit (100) may include a control supply circuit (20), a clock control circuit (30), a control signal test circuit (40), and a scan flip-flop (1). Control supply circuit (20) may receive a control signal (Enable signal), which may be used for enabling a clock signal (CLK) in a gated clock system. A control supply test circuit (40) may provide a signal path that can apply control signal (Enable signal) to scan flip-flop (1) for capturing. In this way, functionality of a combination circuit used for generating a control signal (Enable signal) may be verified.