US Patent 7779319 Input-output device testing including delay tests

Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, where a data value stored in each scan register can be shifted out for analysis. The wrapper circuit also includes two or more update registers to transfer stored data values between itself and an associated scan register. The wrapper circuit also includes a set of combinatorial logic coupled to the scan registers, the update registers and the instruction test processor, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os couple to an external tester.