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US Patent 7712000 ATE architecture and method for DFT oriented testing

Patent 7712000 was granted and assigned to Verigy on May, 2010 by the United States Patent and Trademark Office.

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Patent
Patent

Patent attributes

Current Assignee
Verigy
Verigy
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7712000
Date of Patent
May 4, 2010
Patent Application Number
11589465
Date Filed
October 30, 2006
Patent Citations Received
‌
US Patent 11954461 Autonomously delivering software features
0
‌
US Patent 11748232 System for discovering semantic relationships in computer programs
Patent Primary Examiner
‌
James C. Kerveros
Patent abstract

An ATE system is described for testing one or more DFT testing blocks contained in one or more DUTs when coupled to the ATE system. The ATE system includes hardware resources and software processes under the control of a DPK (Distributed Processing Kernel). The DPK couples the hardware resources and software processes as needed for a first DFT testing block to be enabled for testing only when such resources and processes are available and locked for the first DFT testing block. The DPK is coupled to the first DFT testing blocks via data channels and control channels that are selected as needed for having the first DFT testing block enabled for testing. The channels are under the control of an DUTs-ATE interface which is directed by the DPK for connecting the first DFT testing block to the locked hardware resource and the locked software processes. Each set up process corresponding to any subsequent DFT testing block requesting any hardware resource and any software processes that are already locked for use is paused until such locked resource and locked software processes are unlocked and assigned for having that subsequent DFT testing block enabled for testing.

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