US Patent 7412639 System and method for testing circuitry on a wafer

A system and method in which a plurality of dice on a semiconductor wafer are interconnected to enable efficient testing thereof. In certain embodiments a plurality of dice are interconnected in a manner that enables test data to be communicated from a tester system to a plurality of dice for concurrent testing of such plurality of dice. Depending on the amount of interconnection, all or a portion of each of the plurality of dice may be tested concurrently. In certain embodiments, a plurality of dice are interconnected in a manner that enables test data to be communicated from one die to at least one other die. In certain embodiments, a plurality of dice are interconnected in a manner that enables such dice to be tested concurrently while maintaining a repeatable pattern at the reticle level for fabricating such dice.