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Timothy P. Callahan

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Edits on 15 Dec, 2021
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edited on 15 Dec, 2021
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Patent primary examiner of
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US Patent 7088154 Methods and arrangements for a low power phase-locked loop
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US Patent 7088159 Register controlled delay locked loop and its control method
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US Patent 7088160 Circuit arrangement for regulating a parameter of an electrical signal
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US Patent 7088162 Circuit generating constant narrow-pulse-width bipolarity monocycles
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US Patent 7088163 Circuit for multiplexing a tapped differential delay line to a single output
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US Patent 7091751 Low-power and low-noise comparator having inverter with decreased peak current
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US Patent 7091758 Power-on reset circuit, semiconductor integrated circuit device including the same and method for generating a power-on reset signal
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US Patent 7091760 DLL with adjustable phase shift using processed control signal
‌
US Patent 7091762 Systems and methods for minimizing harmonic interference
‌
US Patent 7091763 Clock generation
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US Patent 7091795 Modulating ramp angle in a digital frequency locked loop
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US Patent 7092479 Ripple counter circuits in integrated circuit devices having fast terminal count capability and methods of operating the same
‌
US Patent 7095254 Method for producing a control signal which indicates a frequency error
‌
US Patent 7095256 Low-power wide dynamic range envelope detector system and method
‌
US Patent 7095265 PVT-compensated clock distribution
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US Patent 7095269 Voltage generator
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US Patent 7095300 Band eliminate filter and communication apparatus
‌
US Patent 7098708 Low-power direct digital synthesizer with analog interpolation
‌
US Patent 7098710 Multi-speed delay-locked loop
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US Patent 7098720 High impedance thermal shutdown circuit
‌
US Patent 7102392 Signal detector for high-speed serdes
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US Patent 7102405 Pulse-width modulation circuit and switching amplifier using the same
‌
US Patent 7102416 High side switching circuit
‌
US Patent 7102421 Dynamically adjustable on-chip supply voltage generation
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US Patent 7102448 Phase frequency detector used in phase locked loop
‌
US Patent 7106106 Clocked comparator circuit
‌
US Patent 7106110 Clock dithering system and method during frequency scaling
‌
US Patent 7106113 Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver
‌
US Patent 7106117 Delayed clock signal generator
‌
US Patent 7106119 Circuit for the temporary interruption of a sync signal
‌
US Patent 7106126 Semiconductor integrated circuit device
‌
US Patent 7109762 Frequency-dividing circuit arrangement and phase locked loop employing such circuit arrangement
‌
US Patent 7109764 PLL clock signal generation circuit
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US Patent 7109765 Programmable phase shift circuitry
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US Patent 7109766 Adjustable frequency delay-locked loop
‌
US Patent 7109774 Delay locked loop (DLL) circuit and method for locking clock delay by using the same
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US Patent 7109778 DC-offset transient response cancel system
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US Patent 7109785 Current source for generating a constant reference current
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US Patent 7113003 Presence indication signal associated with an attachment
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US Patent 7113021 Voltage doubler circuit
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US Patent 7116132 Current feedback amplifiers with separate common-mode and differential-mode inputs
‌
US Patent 7116133 Apparatus and method for adjusting clock skew
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US Patent 7116143 Synchronous clock generator including duty cycle correction
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US Patent 7116144 High bandwidth phase locked loop (PLL)
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US Patent 7116146 Digital DLL device, digital DLL control method, and digital DLL control program
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US Patent 7116147 Circuit and method for interpolative delay
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US Patent 7116149 Duty cycle correction circuit of delay locked loop and the delay locked loop having the duty cycle correction circuit
‌
US Patent 7116150 Clock gater circuit and associated method
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US Patent 7116154 Low power charge pump
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US Patent 7116743 Digital phase lock loop
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US Patent 7116747 Phase-switched dual-mode counter circuit for a frequency synthesizer
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US Patent 7119549 Output calibrator with dynamic precision
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US Patent 7119594 Duty cycle correction circuit of delay locked loop and delay locked loop having the duty cycle correction circuit
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US Patent 7119595 Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof
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US Patent 7119596 Wide-range programmable delay line
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US Patent 7119602 Low-skew single-ended to differential converter
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US Patent 7122953 High pressure discharge lamp and method of manufacturing an electrode feedthrough for such a lamp
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US Patent 7123063 Supply tracking clock multiplier
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US Patent 7123065 Method of improving lock acquisition times in systems with a narrow frequency range
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US Patent 7123067 Voltage-change control circuit and method
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US Patent 7123072 High-accuracy capacitor digital-to-analog converter
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US Patent 7123079 High voltage generator in semiconductor memory device
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US Patent 7123080 Differential amplification input circuit
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US Patent 7123082 Variable time constant circuit and filter circuit using the same
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US Patent 7123085 Rail-to-rail charge pump with replica circuitry
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US Patent 7123679 Counter having improved counting speed
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US Patent 7126391 Power on reset circuits
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US Patent 7126393 Delay circuit with reset-based forward path static delay
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US Patent 7126395 Dynamic slew rate controlling method and device for reducing variance in simultaneous switching output
‌
US Patent 7126398 Method and an apparatus to generate static logic level output
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US Patent 7126402 Signal generation apparatus for supplying timing signal to solid state device
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US Patent 7126404 High resolution digital delay circuit for PLL and DLL
‌
US Patent 7126405 Method and apparatus for a distributed clock generator
‌
US Patent 7126407 Method and device for generating a clock signal with predetermined clock signal properties
‌
US Patent 7126408 Method and apparatus for receiving high-speed signals with low latency
‌
US Patent 7129759 Integrated circuit including an overvoltage protection circuit
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US Patent 7129761 Digital delay-locked loop circuits with hierarchical delay adjustment
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US Patent 7132859 Common-mode current feedback amplifiers
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US Patent 7132860 Differential-mode current feedback amplifiers
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US Patent 7132863 Digital clock frequency doubler
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US Patent 7132864 Method for configuring multiple-output phase-locked loop frequency synthesizer
‌
US Patent 7132866 Method and apparatus for glitch-free control of a delay-locked loop in a network device
‌
US Patent 7132867 High resolution digital loop circuit
‌
US Patent 7132889 Translinear variable gain amplifier
‌
US Patent 7135898 Power-on reset circuit with supply voltage and temperature immunity, ultra-low DC leakage current, and fast power crash reaction
‌
US Patent 7135899 System and method for reducing skew in complementary signals that can be used to synchronously clock a double data rate output
‌
US Patent 7135902 Differential signal generator having controlled signal rise and fall times with built-in test circuitry
‌
US Patent 7135906 Delay circuit and delay synchronization loop device
‌
US Patent 7135907 Clock signal distribution utilizing differential sinusoidal signal pair
‌
US Patent 7135913 Reference voltage generating circuit for integrated circuit
‌
US Patent 7138835 Method and apparatus for an equalizing buffer
‌
US Patent 7138838 Phase locked loop
‌
US Patent 7138839 Phase-locked loops
‌
US Patent 7138844 Variable delay circuitry
‌
US Patent 7138845 Method and apparatus to set a tuning range for an analog delay
‌
US Patent 7138849 Phase mixer that compensates for frequency variations and PVT variations and a control method thereof
‌
US Patent 7138850 High-gain synchronizer circuitry and methods
‌
US Patent 7138877 PLL and method for providing a single/multiple adjustable frequency range
‌
US Patent 7142025 Phase difference detector, particularly for a PLL circuit
‌
US Patent 7142026 Delay locked loop and its control method for correcting a duty ratio of a clock signal
‌
US Patent 7142032 Tunable delay circuit
‌
US Patent 7142035 Signal generator circuit and level shifter with signal generator circuit
‌
US Patent 7142046 Current sharing using gate modulated diodes
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US Patent 7142627 Counting scheme with automatic point-of-reference generation
‌
US Patent 7145367 Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector
‌
US Patent 7145371 Variable frequency generator
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US Patent 7145373 Frequency-controlled DLL bias
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US Patent 7145383 Voltage supply with low power and leakage current
‌
US Patent 7148733 Variable delay circuit with faster delay data update
‌
US Patent 7148738 Systems, devices, and methods for providing control signals
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US Patent 7148741 Current supply circuit and method for supplying current to a load
‌
US Patent 7154305 Periodic electrical signal frequency monitoring systems and methods
‌
US Patent 7154312 Apparatus for generating internal clock signal
‌
US Patent 7154316 Circuit for controlling pulse width
‌
US Patent 7154323 Delay circuit and control method of the delay circuit
‌
US Patent 7157948 Method and apparatus for calibrating a delay line
‌
US Patent 7157949 Delay locked loop capable of preventing false lock and method thereof
‌
US Patent 7157952 Systems and methods for implementing delay line circuitry
‌
US Patent 7157953 Circuit for and method of employing a clock signal
‌
US Patent 7157954 Semiconductor type two phase locked loop filter
‌
US Patent 7157962 Charge pump output device with leakage cancellation
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US Patent 7161395 Static frequency divider with low power supply
‌
US Patent 7161396 CMOS power on reset circuit
‌
US Patent 7161402 Programmable delay locked loop
‌
US Patent 7161409 Precision, low drift, closed loop voltage reference
‌
US Patent 7161417 Loop filter and method for generating stable control voltage of the same
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US Patent 7164299 Output buffer circuit having pre-emphasis function
‌
US Patent 7164306 Composite multiplexer circuit and chip component, high-frequency module and radio communication apparatus using the same
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US Patent 7164307 Bias generator for body bias
‌
US Patent 7167027 Latch-type level converter and receiver circuit accurately amplifying low-amplitude signals and receiving common-mode input signals higher than a supply voltage
‌
US Patent 7167031 Synchronizing circuit provided with hysteresis phase comparator
‌
US Patent 7167035 Delay circuitry and method therefor
‌
US Patent 7167037 Charge pump bias network
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US Patent 7167043 Decoupling circuit for co-packaged semiconductor devices
‌
US Patent 7170323 Delay locked loop harmonic detector and associated method
‌
US Patent 7170325 Circuit for controlling a delay time of input pulse and method of controlling the same
‌
US Patent 7170331 Delay circuit
‌
US Patent 7170337 Low voltage wide ratio current mirror
‌
US Patent 7170354 Oscillator circuit with laser-trimmable load impedance
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US Patent 7173461 Self-biased phased-locked loop
‌
US Patent 7173462 Second order delay-locked loop for data recovery
‌
US Patent 7173463 Generating multi-phase clock signals using hierarchical delays
‌
US Patent 7173465 High-speed, current-driven latch
‌
US Patent 7173468 Multiple-input, single-exit delay line architecture
‌
US Patent 7173469 Clocking system and method for a memory
‌
US Patent 7173470 Clock sources and methods with reduced clock jitter
‌
US Patent 7173473 Level-shifting circuitry having “high” output impedance during disable mode
‌
US Patent 7173481 CMOS reference voltage circuit
‌
US Patent 7176731 Variation tolerant charge leakage correction circuit for phase locked loops
‌
US Patent 7176734 Clock signal generation circuits and methods using phase mixing of even and odd phased clock signals
‌
US Patent 7176736 High-speed, current driven latch
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US Patent 7176738 Method and apparatus for clock generation
‌
US Patent 7176743 Driver circuit capable of providing rise and fall transitions that step smoothly in the transition regions
‌
US Patent 7180334 Apparatus and method for decreasing the lock time of a lock loop circuit
‌
US Patent 7180340 Frequency multiplier capable of adjusting duty cycle of a clock and method used therein
‌
US Patent 7180341 Variable division method and variable divider
‌
US Patent 7180344 Phase locked loop and method for trimming a loop filter
‌
US Patent 7180345 Apparatus and a method to provide time-based edge-rate compensation
‌
US Patent 7180346 Duty cycle correcting circuits having a variable gain and methods of operating the same
‌
US Patent 7180347 Systems and methods for minimizing harmonic interference
‌
US Patent 7180348 Circuit and method for storing data in operational and sleep modes
‌
US Patent 7180349 Frequency divider system
‌
US Patent 7180352 Clock recovery using clock phase interpolator
‌
US Patent 7180353 Apparatus and method for low power clock distribution
‌
US Patent 7180354 Receiver having full signal path differential offset cancellation capabilities
‌
US Patent 7180362 Semiconductor device with pump circuit
‌
US Patent 7180974 Frequency division method and device
‌
US Patent 7183812 Stable systems for comparing and converting signals
‌
US Patent 7183815 Drive apparatus for CCD image sensor
‌
US Patent 7183820 Phase synchronous circuit
‌
US Patent 7183829 Semiconductor device including a plurality of circuit blocks provided on a chip and having different functions
‌
US Patent 7183831 Clock switching circuit
‌
US Patent 7183835 Semiconductor device which realizes a short-circuit protection function without shunt resistor, and semiconductor device module
‌
US Patent 7183837 Charge pump circuit with latch-up prevention
‌
US Patent 7183838 Semiconductor device having internal power supply voltage dropping circuit
‌
US Patent 7183876 Variable coupling factor directional coupler
‌
US Patent 7187215 High dynamic range current-mode track-and-hold circuit
‌
US Patent 7187216 Phase selectable divider circuit
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US Patent 7187220 Memory clock slowdown
‌
US Patent 7187226 Anti-cross conduction drive control circuit and method
‌
US Patent 7187227 Driver circuit
‌
US Patent 7187228 Method of programming an antifuse
‌
US Patent 7190195 Input circuit and output circuit
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US Patent 7190200 Delay locked loop capable of performing reliable locking operation
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US Patent 7190201 Method and apparatus for initializing a delay locked loop
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US Patent 7190202 Trim unit having less jitter
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US Patent 7190203 Memory device having a duty ratio corrector
‌
US Patent 7190204 Logical circuit
‌
US Patent 7190207 One way conductor
‌
US Patent 7190213 Digital time constant tracking technique and apparatus
‌
US Patent 7193449 Method and apparatus for generating multi-phase signal
‌
US Patent 7193450 Load sensing buffer circuit with controlled switching current noise (di/dt)
‌
US Patent 7193456 Current conveyor circuit with improved power supply noise immunity
‌
US Patent 7196554 Integrated clock supply chip for a memory module, memory module comprising the integrated clock supply chip, and method for operating the memory module under test conditions
‌
US Patent 7196558 Frequency divider with slip
‌
US Patent 7196571 Semiconductor integrated circuit device
‌
US Patent 7196572 Integrated circuit for stabilizing a voltage
‌
US Patent 7197104 Minimum gate delay edge counter
‌
US Patent 7199626 Delay-locked loop device capable of anti-false-locking and related methods
‌
US Patent 7199628 Power supply apparatus for delay locked loop and method thereof
‌
US Patent 7199629 Circuit having delay locked loop for correcting off chip driver duty distortion
‌
US Patent 7199630 Delay locked loops and methods using ring oscillators
‌
US Patent 7199633 Electric pulse generator and method for generating short electric pulses
‌
US Patent 7199637 Rectifier circuit without alternating-current feedback
‌
US Patent 7199640 Bi-directional double NMOS switch
‌
US Patent 7199646 High PSRR, high accuracy, low power supply bandgap circuit
‌
US Patent 7202707 High frequency binary phase detector
‌
US Patent 7202712 Multiphase resonant pulse generators
‌
US Patent 7202713 Power-on bias circuit using Schmitt Trigger
‌
US Patent 7202717 Chopped charge pump
‌
US Patent 7202719 Method and apparatus for frequency synthesis
‌
US Patent 7202720 Delay locked loop having a duty cycle correction circuit
‌
US Patent 7202721 Delay locked loop and semiconductor memory device having the same
‌
US Patent 7202725 Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device
‌
US Patent 7205800 Clock frequency divider circuit
‌
US Patent 7205803 High speed fully scaleable, programmable and linear digital delay circuit
‌
US Patent 7205804 Methods and system for reducing effects of digital loop dead zones
‌
US Patent 7205811 Methods and apparatus for maintaining desired slope of clock edges in a phase interpolator using an adjustable bias
‌
US Patent 7205814 Pulse generator
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US Patent 7205829 Clocked standby mode with maximum clock frequency
‌
US Patent 7208984 CMOS driver with minimum shoot-through current
‌
US Patent 7208985 Semiconductor device for controlling switching power supply
‌
US Patent 7208989 Synchronous clock generator including duty cycle correction
‌
US Patent 7208997 Charge pump power supply circuit
‌
US Patent 7208999 Step-down circuit with stabilized output voltage
‌
US Patent 7209009 Controlling a voltage controlled oscillator in a bang-bang phase locked loop
‌
US Patent 7212043 Line regulator with high bandwidth (BW) and high power supply rejection ration (PSRR) and wide range of output current
‌
US Patent 7212045 Double frequency signal generator
‌
US Patent 7212046 Power-up signal generating apparatus
‌
US Patent 7212048 Multiple phase detection for delay loops
‌
US Patent 7212052 Jitter suppressing delay locked loop circuits and related methods
‌
US Patent 7212053 Measure-initialized delay locked loop with live measurement
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US Patent 7212054 DLL with adjustable phase shift using processed control signal
‌
US Patent 7212055 Open-loop digital duty cycle correction circuit without DLL
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US Patent 7212057 Measure-controlled circuit with frequency control
‌
US Patent 7212066 Charge pump circuit
‌
US Patent 7215162 Start signal outputting circuit
‌
US Patent 7215166 DLL circuit with delay equal to one clock cycle
‌
US Patent 7215169 Current-controlled CMOS logic family
‌
US Patent 7215174 Method and apparatus for implementing a radiation hardened N-channel transistor with the use of non-radiation hardened transistors
‌
US Patent 7218155 Techniques for controlling on-chip termination resistance using voltage range detection
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US Patent 7218156 Supply tracking clock multiplier
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US Patent 7218161 Substantially temperature independent delay chain
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US Patent 7218699 Frequency divider
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US Patent 7221190 Differential comparator with extended common mode voltage range
‌
US Patent 7221193 On-chip termination with calibrated driver strength
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US Patent 7221202 Delay-locked loop with reduced susceptibility to false lock
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US Patent 7221206 Integrated circuit device having clock signal output circuit
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US Patent 7221214 Delay value adjusting method and semiconductor integrated circuit
‌
US Patent 7224199 Circuit and method for digital delay and circuits incorporating the same
‌
US Patent 7224204 Method and circuit for driving a gate of a MOS transistor negative
‌
US Patent 7224208 Voltage regulator which outputs a predetermined direct-current voltage with its extreme variation restrained
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US Patent 7227386 Phase locked loop lock-detection circuit
‌
US Patent 7227387 Measuring pulse edge delay value relative to a clock using multiple delay devices to address a memory to access the delay value
‌
US Patent 7227395 High-performance memory interface circuit architecture
‌
US Patent 7227397 System, method and circuits for generating a signal
‌
US Patent 7227398 High resolution digital delay circuit for PLL and DLL
‌
US Patent 7230458 Delta/sigma frequency discriminator
‌
US Patent 7230459 Static frequency divider for microwave applications
‌
US Patent 7230461 Retiming circuits for phase-locked loops
‌
US Patent 7230462 Clock signal synchronizing device, and clock signal synchronizing method
‌
US Patent 7230464 Closed-loop delay compensation for driver
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US Patent 7230468 Systems and methods for providing distributed control signal redundancy among electronic circuits
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US Patent 7230471 Charge pump circuit of LCD driver including driver having variable current driving capability
‌
US Patent 7233175 Amplitude limiting circuit
‌
US Patent 7233181 Prescaler circuit
‌
US Patent 7233187 Dual-mode pulse generator
‌
US Patent 7233195 Generator for supplying reference voltage and reference current of stable level regardless of temperature variation
‌
US Patent 7236028 Adaptive frequency variable delay-locked loop
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US Patent 7236034 Self correcting scheme to match pull up and pull down devices
‌
US Patent 7236035 Semiconductor device adapted to minimize clock skew
‌
US Patent 7236036 Apparatus and method for generating pulses
‌
US Patent 7236037 Alternating clock signal generation for delay loops
‌
US Patent 7236039 Spread spectrum clock generating apparatus
‌
US Patent 7236042 Fuse trimming circuit
‌
US Patent 7236045 Bias generator for body bias
‌
US Patent 7239186 System and method for power-on control of input/output drivers
‌
US Patent 7239198 Single gate oxide differential receiver and method
‌
US Patent 7239216 Semiconductor memory device with data bus scheme for reducing high frequency noise
‌
US Patent 7242223 Clock frequency monitor
‌
US Patent 7242224 Continuous, wide-range frequency synthesis and phase tracking methods and apparatus
‌
US Patent 7242229 Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode
‌
US Patent 7242230 Microprocessor with power saving clock
‌
US Patent 7242232 Internal signal replication device and method
‌
US Patent 7242238 Drive circuit for voltage driven type semiconductor element
‌
US Patent 7242261 Voltage control for clock generating circuit
‌
US Patent 7245164 Radio frequency doubler
‌
US Patent 7245170 Attenuator and portable telephone terminal apparatus using the same
‌
US Patent 7248089 Method of establishing a PWM-modulated output signal representation
‌
US Patent 7248091 Semiconductor device having delay drift compensation circuit that compensates for delay drift caused by temperature and voltage variations in clock tree
‌
US Patent 7248102 Internal reference voltage generation for integrated circuit testing
‌
US Patent 7250794 Voltage source converter
‌
US Patent 7250798 Synchronous clock generator including duty cycle correction
‌
US Patent 7256623 Frequency programmable feed-forward oscillator and triangle wave generator
‌
US Patent 7256643 Device and method for generating a low-voltage reference
‌
US Patent 7268594 Direct digital synthesis with low jitter
‌
US Patent 7268597 Self-initializing frequency divider
Edits on 22 Nov, 2021
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edited on 22 Nov, 2021
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Infobox
Patent primary examiner of
‌
US Patent 7268594 Direct digital synthesis with low jitter
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7268597 Self-initializing frequency divider
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7256643 Device and method for generating a low-voltage reference
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7256623 Frequency programmable feed-forward oscillator and triangle wave generator
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7250798 Synchronous clock generator including duty cycle correction
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7250794 Voltage source converter
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Golden AI
edited on 22 Nov, 2021
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7248102 Internal reference voltage generation for integrated circuit testing
Golden AI profile picture
Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7248089 Method of establishing a PWM-modulated output signal representation
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7245164 Radio frequency doubler
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7245170 Attenuator and portable telephone terminal apparatus using the same
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7242261 Voltage control for clock generating circuit
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7242230 Microprocessor with power saving clock
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Golden AI
edited on 22 Nov, 2021
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7242238 Drive circuit for voltage driven type semiconductor element
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7242232 Internal signal replication device and method
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7242223 Clock frequency monitor
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7242224 Continuous, wide-range frequency synthesis and phase tracking methods and apparatus
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Golden AI
edited on 22 Nov, 2021
Edits made to:
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Infobox
Patent primary examiner of
‌
US Patent 7239216 Semiconductor memory device with data bus scheme for reducing high frequency noise

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