US Patent 7116144 High bandwidth phase locked loop (PLL)

A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a re-sampling circuit operable to re-sample one or more digital pulses of the divided signal using one or more phase signals if a multiplication factor of the frequency multiplier does not divide evenly into the integer divisor.