US Patent 7154316 Circuit for controlling pulse width

Provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supplying various CAS latencies by means of including: a mode register set for setting a plurality of CAS latencies according to an operation frequency by a command inputted from a chip set; and a pulse generation circuit for generating a pulse having a variable width by using a delay time according to the plurality of CAS latencies set in the mode register set.