US Patent 7161402 Programmable delay locked loop

A delay lock loop (DLL) system includes a master DLL and at least one slave DLL. The master DLL comprises a master delay line, a phase detector, and a loop controller. The master delay line of the master DLL includes four quarter cycle delay lines (QCDL). The slave DLL comprises a delay line and a fractional bit delay element. The delay line of the slave DLL is controlled by the slave delay line control signal generated by the loop controller of the master DLL. The final output of the slave DLL is formed such that the output of the delay line of the slave DLL is corrected by the fractional bit delay generated by the factional bit delay element such that the final output of the slave DLL has a finer delay line resolution than the one of the output of the delay line of the slave DLL.