Patent attributes
A digital feedback loop circuit achieves a resolution as good as the intrinsic resolution of the delay element of the circuit, notwithstanding the presence of a feedback counter/divider of integer value N that might otherwise be expected to multiply the minimum resolution by N. Output altering circuitry is used to alter the error feedback signal for M out of every N feedback cycles in such a way that the overall delay over N cycles can be controlled to within the resolution of the delay element. In one embodiment, the output altering circuitry includes a second counter whose maximum value is controllable and that outputs a signal whose value changes after its current maximum value has been reached. In another embodiment, the output altering circuitry includes a lookup table preloaded with sequences of output signals, with the sequence selected by a controller.
