US Patent 7154323 Delay circuit and control method of the delay circuit

A delay circuit is constructed by connecting taps TAP0–n for providing with a unit delay time (τ) in series on multiple stages. Each tap has the same configuration and an objective signal is inputted to a signal input terminal IN1. The output terminal of a preceding stage tap is connected to a between-stages connecting terminal IN2. An output terminal O is connected to the between-stages connecting terminal of a next stage tap. The signal input terminal and the between-stages connecting terminal are connected to one input terminal of NAND gates 1, 2 and a tap selection signal is inputted to the other input terminal. The output terminal is connected to a NAND gate 3. One of the NAND gates 1, 2 functions as a logical inversion gate corresponding to a tap selection signal so as to enable propagation of the signal. At this time, in the other NAND gate, the output signal is fixed to high level and the NAND gate 3 also functions as a logical inversion gate. The objective signal is propagated by the NAND gates 1, 3 and the preceding stage signal is propagated by the NAND gates 2, 3. By constructing the NAND gates 1, 2 with the same structure, the unit delay time (τ) can be matched accurately.