Patent attributes
A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming portion of an integrated circuit to operate at a relatively higher average clock rate than a more power consuming portion operating at a relatively lower clock rate, by adjusting the duration of the cycles of the higher frequency clock. The adjustment may be according to the supply voltage changes that result from logic switching activity of the more power consuming portion, and may be performed in a manner that substantially matches the delay behavior of the logic. The phase of the higher frequency clock remains locked to the lower frequency clock. An embodiment of the present invention may reduce the area and cost of an integrated circuit by minimizing the need for other on-chip power supply noise mitigation approaches, while also improving device throughput and performance.
