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Verigy
Verigy is a Singapore-based semiconductor company founded in 2006.
Overview
Structured Data
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Activity
All edits
Edits on 4 Nov, 2022
"Edit from table cell"
Semyon Kolychev
edited on 4 Nov, 2022
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+1
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Glassdoor ID
40792
Edits on 14 Aug, 2022
B.R WON
edited on 14 Aug, 2022
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+2
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Crunchbase URL
https://www.crunchbase.com/organization/verigy
Pitchbook URL
https://pitchbook.com/profiles/company/41612-14
Edits on 23 Jul, 2022
"clean up phone number value"
Golden AI
edited on 23 Jul, 2022
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Phone number
650-752-5503
Phone number
+16507525503
Edits on 16 Jun, 2022
"Entity importer update"
Golden AI
edited on 16 Jun, 2022
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+1
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Is a
Organization
Edits on 24 May, 2022
Петров Даниил
edited on 24 May, 2022
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+1
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B2X
B2B
Edits on 11 May, 2022
Patrick Pum
edited on 11 May, 2022
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+10
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Acquired company
Touchdown Technologies
Acquirer
Advantest
Legal name
Verigy Ltd.
Company Operating Status
Active
Country
Singapore
Full address
NO. 1 YISHUN AVE. 7, SINGAPORE, Singapore, 768923
Industry
Loading...
Number of Employees (ranges)
1,000 – 4,999
Phone number
650-752-5503
Previous name
Verigy Pte. Ltd.
Edits on 8 Apr, 2022
"Patent autocalculation"
Golden AI
edited on 8 Apr, 2022
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+1
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Patents assigned (count)
133
Edits on 14 Dec, 2021
"Remove inverse infobox"
Golden AI
edited on 14 Dec, 2021
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Patents
US Patent 7106081 Parallel calibration system for a test device
US Patent 7112977 Construction and use of dielectric plate for mating test equipment to a load board of a circuit tester
US Patent 7131046 System and method for testing circuitry using an externally generated signature
US Patent 7137052 Methods and apparatus for minimizing current surges during integrated circuit testing
US Patent 7137083 Verification of integrated circuit tests using test simulation and integrated circuit simulation with simulated failure
US Patent 7146539 Systems and methods for testing a device-under-test
US Patent 7147499 Zero insertion force printed circuit assembly connector system and method
US Patent 7180392 Coaxial DC block
US Patent 7181358 Method, apparatus and database using a map of linked data nodes for storing test numbers
US Patent 7181660 Reconstruction of non-deterministic algorithmic tester stimulus used as input to a device under test
US Patent 7181663 Wireless no-touch testing of integrated circuits
US Patent 7184469 Systems and methods for injection of test jitter in data bit-streams
US Patent 7190217 System, method and apparatus for providing ground separation between different environments
US Patent 7190583 Self contained, liquid to air cooled, memory test engineering workstation
US Patent 7193854 Using a leaf spring to attach clamp plates with a heat sink to both sides of a component mounted on a printed circuit assembly
US Patent 7194373 Device testing control
US Patent 7206710 Incremental generation of calibration factors for automated test equipment
US Patent 7213803 Clamp and method for operating same
US Patent 7218095 Method and apparatus for electromagnetic interference shielding in an automated test system
US Patent 7231573 Delay management system
US Patent 7240259 Pin coupler for an integrated circuit tester
US Patent 7248660 Transition tracking
US Patent 7250892 Data converter with integrated MEMS resonator clock
US Patent 7251798 Method and apparatus for quantifying the timing error induced by crosstalk between signal paths
US Patent 7252555 Pin connector
US Patent 7253760 Method for adjusting signal generator and signal generator
US Patent 7254760 Methods and apparatus for providing scan patterns to an electronic device
US Patent 7260493 Testing a device under test by sampling its clock and data signal
US Patent 7262620 Resource matrix, system, and method for operating same
US Patent 7263601 Sequencer unit with instruction buffering
US Patent 7274202 Carousel device, system and method for electronic circuit tester
US Patent 7279919 Systems and methods of allocating device testing resources to sites of a probe card
US Patent 7280934 Method for test of electronic component
US Patent 7281181 Systems, methods and computer programs for calibrating an automated circuit test system
US Patent 7290189 Compilation of calibration information for plural testflows
US Patent 7315170 Calibration apparatus and method using pulse for frequency, phase, and delay characteristic
US Patent 7320617 Electrical coupling apparatus and method
US Patent 7321634 Method and apparatus for variable sigma-delta modulation
US Patent 7321967 System and method for configuring capabilities of printed circuit boards
US Patent 7321999 Methods and apparatus for programming and operating automated test equipment
US Patent 7323897 Mock wafer, system calibrated using mock wafer, and method for calibrating automated test equipment
US Patent 7328137 Methods and systems for derivation of missing data objects from test data
US Patent 7333042 Method and system for digital to analog conversion using multi-purpose current summation
US Patent 7339844 Memory device fail summary data reduction for improved redundancy analysis
US Patent 7340688 Application of paging to a dataset, graphical display window and graphical scrollbar grip
US Patent 7346102 Channel with domain crossing
US Patent 7355378 Source synchronous sampling
US Patent 7373360 Methods and apparatus that use contextual test number factors to assign test numbers
US Patent 7378860 Wafer test head architecture and method of use
US Patent 7378862 Method and apparatus for eliminating automated testing equipment index time
US Patent 7379856 Modeling an electronic device
US Patent 7386777 Systems and methods for processing automatically generated test patterns
US Patent 7397235 Pin electronic for automatic testing of integrated circuits
US Patent 7403874 Method and system for prioritizing formatting actions of a number of data formatters
US Patent 7404109 Systems and methods for adaptively compressing test data
US Patent 7404121 Method and machine-readable media for inferring relationships between test results
US Patent 7412639 System and method for testing circuitry on a wafer
US Patent 7414558 Digital to analog conversion using summation of multiple DACs
US Patent 7415479 Method and apparatus for assigning test numbers
US Patent 7420385 System-on-a-chip pipeline tester and method
US Patent 7421360 Method and apparatus for handling a user-defined event that is generated during test of a device
US Patent 7421632 Mapping logic for controlling loading of the select ram of an error data crossbar multiplexer
US Patent 7434118 Parameterized signal conditioning
US Patent 7444566 Memory device fail summary data reduction for improved redundancy analysis
US Patent 7452214 Interconnect assemblies, and methods of forming interconnects, between conductive contact bumps and conductive contact pads
US Patent 7457729 Model based testing for electronic devices
US Patent 7459921 Method and apparatus for a paddle board probe card
US Patent 7480583 Methods and apparatus for testing a circuit
US Patent 7482817 Method and an apparatus for measuring the input threshold level of device under test
US Patent 7501844 Liquid cooled DUT card interface for wafer sort probing
US Patent 7502974 Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets
US Patent 7512858 Method and system for per-pin clock synthesis of an electronic device under test
US Patent 7518454 Operational amplifier selecting one of inputs, and an amplifying apparatus using the OP amplifier the verification method
US Patent 7519827 Provisioning and use of security tokens to enable automated test equipment
US Patent 7519887 Apparatus for storing and formatting data
US Patent 7536663 Method and apparatus for quantifying the timing error induced by an impedance variation of a signal path
US Patent 7541824 Forced air cooling of components on a probecard
US Patent 7550988 Test device with test parameter adaptation
US Patent 7552530 Method of manufacturing a PCB having improved cooling
US Patent 7555639 Method for configuring a data formatting process using configuration values of a highest priority for each of a number of configuration keys storing in several configuration layers
US Patent 7574185 Method and apparatus for generating a phase-locked output signal
US Patent 7581148 System, method and apparatus for completing the generation of test records after an abort event
US Patent 7584395 Systems, methods and apparatus for synthesizing state events for a test data stream
US Patent 7587015 Asynchronous digital data capture
US Patent 7590903 Re-configurable architecture for automated test equipment
US Patent 7614286 Methods for sampling equipment and fluid conditions
US Patent 7617503 Method and apparatus for determining which of two computer processes should perform a function X
US Patent 7644213 Resource access manager for controlling access to a limited-access resource
US Patent 7650547 Apparatus for locating a defect in a scan chain while testing digital logic
US Patent 7676347 Systems and methods for accumulation of summaries of test data
US Patent 7696744 Screw-less latching system for securing load boards
US Patent 7707468 System and method for electronic testing of multiple memory devices
US Patent 7711524 Estimating boundaries of Schmoo plots
US Patent 7712000 ATE architecture and method for DFT oriented testing
US Patent 7717715 System, method and apparatus using at least one flex circuit to connect a printed circuit board and a socket card assembly that are oriented at a right angle to one another
US Patent 7720793 Method and system for selectively processing test data using subscriptions in a multi-formatter architecture
US Patent 7734848 System and method for frequency offset testing
US Patent 7743304 Test system and method for testing electronic devices using a pipelined testing architecture
US Patent 7750650 Solid high aspect ratio via hole used for burn-in boards, wafer sort probe cards, and package test load boards with electronic circuitry
US Patent 7768278 High impedance, high parallelism, high temperature memory test system architecture
US Patent 7782242 Time-to-digital conversion with delay contribution determination of delay elements
US Patent 7791525 Time-to-digital conversion with calibration pulse injection
US Patent 7797599 Diagnostic information capture from logic devices with built-in self test
US Patent 7812626 High density interconnect system for IC packages and interconnect assemblies
US Patent 7821254 Method and apparatus for improving load time for automated test equipment
US Patent 7823128 Apparatus, system and/or method for combining multiple tests to a single test in a multiple independent port test environment
US Patent 7825650 Automated loader for removing and inserting removable devices to improve load time for automated test equipment
US Patent 7827452 Error catch RAM support using fan-out/fan-in matrix
US Patent 7847716 Asynchronous sigma-delta digital-analog converter
US Patent 7853828 Graphically extensible, hardware independent method to inspect and modify state of test equipment
US Patent 7853846 Locating hold time violations in scan chains by generating patterns on ATE
US Patent 7859277 Apparatus, systems and methods for processing signals between a tester and a plurality of devices under test at high temperatures and with single touchdown of a probe array
US Patent 7865788 Dynamic mask memory for serial scan testing
US Patent 7872482 High density interconnect system having rapid fabrication cycle
US Patent 7884634 High density interconnect system having rapid fabrication cycle
US Patent 7893695 Apparatus, method, and computer program for obtaining a time-domain-reflection response-information
US Patent 7921344 Multi-stage data processor with signal repeater
US Patent 7921381 Method and apparatus for displaying test data
US Patent 7924043 Method and product for testing a device under test
US Patent 7928755 Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test
US Patent 7930603 Feature-oriented test program development and execution
US Patent 7934710 Clamp and method for operating same
US Patent 7952373 Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies
US Patent 8005633 Excitation signal generator for improved accuracy of model-based testing
US Patent 8006149 System and method for device performance characterization in physical and logical domains with AC SCAN testing
US Patent 8008933 System and method for baseband calibration
US Patent 8010856 Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains
US Patent 8010933 Source synchronous timing extraction, cyclization and sampling
Edits on 8 Dec, 2021
Golden AI
edited on 8 Dec, 2021
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Patents
US Patent 8010933 Source synchronous timing extraction, cyclization and sampling
Golden AI
edited on 8 Dec, 2021
Edits made to:
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+1
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Patents
US Patent 8010856 Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains
Golden AI
edited on 8 Dec, 2021
Edits made to:
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+1
properties)
Infobox
Patents
US Patent 8008933 System and method for baseband calibration
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox
(
+1
properties)
Infobox
Patents
US Patent 8006149 System and method for device performance characterization in physical and logical domains with AC SCAN testing
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox
(
+1
properties)
Infobox
Patents
US Patent 8005633 Excitation signal generator for improved accuracy of model-based testing
Edits on 7 Dec, 2021
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox
(
+1
properties)
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Patents
US Patent 7952373 Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox
(
+1
properties)
Infobox
Patents
US Patent 7934710 Clamp and method for operating same
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox
(
+1
properties)
Infobox
Patents
US Patent 7930603 Feature-oriented test program development and execution
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox
(
+1
properties)
Infobox
Patents
US Patent 7928755 Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test
Edits on 7 Dec, 2021
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox
(
+1
properties)
Infobox
Patents
US Patent 7924043 Method and product for testing a device under test
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox
(
+1
properties)
Infobox
Patents
US Patent 7921381 Method and apparatus for displaying test data
Golden AI
edited on 7 Dec, 2021
Edits made to:
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(
+1
properties)
Infobox
Patents
US Patent 7921344 Multi-stage data processor with signal repeater
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