Powertech Technology

US Patent 11127699 Chip package structure and manufacturing method thereof

US Patent 11133291 Chip package structure with multi-chip stack

US Patent 11094654 Package structure and method of manufacturing the same

US Patent 11088080 Chip package structure using silicon interposer as interconnection bridge

US Patent 11088100 Semiconductor package and manufacturing method thereof

US Patent 11158608 Semiconductor package including offset stack of semiconductor dies between first and second redistribution structures, and manufacturing method therefor

US Patent 11164771 Wafer transferring device

US Patent 11171106 Semiconductor package structure with circuit substrate and manufacturing method thereof

US Patent 7408245 IC package encapsulating a chip under asymmetric single-side leads

US Patent 7432601 Semiconductor package and fabrication process thereof

US Patent 7479704 Substrate improving immobilization of ball pads for BGA packages

US Patent 7547974 Wiring substrate with improvement in tensile strength of traces

US Patent 7549568 Method of forming identification code for wire-bonding machines

US Patent 7564123 Semiconductor package with fastened leads

US Patent 7566963 Stacked assembly of semiconductor packages with fastening lead-cut ends of leadframe

US Patent 7569935 Pillar-to-pillar flip-chip assembly

US Patent 7605018 Method for forming a die-attach layer during semiconductor packaging processes

US Patent 7605462 Universal substrate for a semiconductor device having selectively activated fuses

US Patent 7619305 Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking

US Patent 7619307 Leadframe-based semiconductor package having arched bend in a supporting bar and leadframe for the package

US Patent 7622794 COL (Chip-On-Lead) multi-chip package

US Patent 7633143 Semiconductor package having plural chips side by side arranged on a leadframe

US Patent 7633160 Window-type semiconductor package to avoid peeling at moldflow entrance

US Patent 7663204 Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications

US Patent 7667306 Leadframe-based semiconductor package

US Patent 7675186 IC package with a protective encapsulant and a stiffening encapsulant

US Patent 7691676 Mold array process for semiconductor packages

US Patent 7692311 POP (package-on-package) device encapsulating soldered joints between external leads

US Patent 7692313 Substrate and semiconductor package for lessening warpage

US Patent 7696618 POP (package-on-package) semiconductor device

US Patent 7723828 Semiconductor package with leads on a chip having multi-row of bonding pads

US Patent 7732921 Window type BGA semiconductor package and its substrate

US Patent 7750444 Lead-on-chip semiconductor package and leadframe for the package

US Patent 7776649 Method for fabricating wafer level chip scale packages

US Patent 7786568 Window BGA semiconductor package

US Patent 7812430 Leadframe and semiconductor package having downset baffle paddles

US Patent 7821112 Semiconductor device with wire-bonding on multi-zigzag fingers

US Patent 7838967 Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips

US Patent 7879648 Fabrication method for high pin count chip package

US Patent 7884472 Semiconductor package having substrate ID code and its fabricating method

US Patent 7902663 Semiconductor package having stepwise depression in substrate

US Patent 7902666 Flip chip device having soldered metal posts by surface mounting

US Patent 7913539 Apparatus for drop testing and method utilizing the same

US Patent 7919715 Circuit board ready to slot

US Patent 7919851 Laminate substrate and semiconductor package utilizing the substrate

US Patent 7927919 Semiconductor packaging method to save interposer

US Patent 7952168 Substrate strip for semiconductor packages

US Patent 7972904 Wafer level packaging method

US Patent 7985662 Method for manufacturing dies formed with a dielectric layer