Patent attributes
A fabrication method for a high pin count chip package is provided herein. First, a lead frame is provided, wherein the lead frame has a chip carrier and a plurality of first lead pins configured around the chip carrier. A first channel is formed on the first lead pins to define a first contact portions and a second contact portion. A die mounting process, a wire bonding process, and a molding process are performed in turn, wherein the molding compound is utilized to encapsulate the chip, the wires, and the first channel. After that, a backside sawing process is performed to electrically isolate the first contact portions and the second contact portions. The present invention achieves high pin count chip package without changing the appearance and size of product and the reasonable width limitation of the lead pins.
