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Phung My Chung

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Edits on 14 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 14 Dec, 2021
Edits made to:
Infobox (-105 properties)
Infobox
Patent primary examiner of
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US Patent 7089474 Method and system for providing interactive testing of integrated circuits
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US Patent 7089475 Error correction of data across an isolation barrier
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US Patent 7093181 Apparatus and method for transmitting/receiving error detection information in a communication system
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US Patent 7096404 Forward error correction scheme for data channels using universal turbo codes
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US Patent 7107500 Test mode circuit of semiconductor memory device
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US Patent 7107502 Diagnostic method for detection of multiple defects in a Level Sensitive Scan Design (LSSD)
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US Patent 7107515 Radiation hard divider via single bit correction
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US Patent 7117404 Test circuit for testing a synchronous memory circuit
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US Patent 7117407 Method for testing a semiconductor memory having a plurality of memory banks
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US Patent 7117415 Automated BIST test pattern sequence generator software system and method
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US Patent 7117417 Method for generating clock corrections for a wide-area or global differential GPS system
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US Patent 7117418 Soft input-soft output forward error correction decoding for turbo codes
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US Patent 7120842 Mechanism to enhance observability of integrated circuit failures during burn-in tests
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US Patent 7134060 Semiconductor integrated circuit including operation test circuit and operation test method thereof
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US Patent 7134070 Checksum determination
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US Patent 7139942 Method and apparatus for memory redundancy and recovery from uncorrectable errors
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US Patent 7139947 Test access port
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US Patent 7143325 Method for testing circuit units to be tested by means of majority decisions and test device for performing the method
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US Patent 7143336 Decoding parallel concatenated parity-check code
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US Patent 7146552 Apparatus and method for performing coding and rate matching in a CDMA mobile communication system
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US Patent 7149943 System for flexible embedded Boundary Scan testing
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US Patent 7152195 Scan test circuit
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US Patent 7155645 System and method for testing memory while an operating system is active
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US Patent 7155650 IC with separate scan paths and shift states
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US Patent 7155658 CRC calculation for data with dynamic header
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US Patent 7155661 Apparatus and method for transmitting/receiving error detection information in a communication system
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US Patent 7159155 Error rate control apparatus
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US Patent 7159162 Semi-reliable ARQ method and device thereof
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US Patent 7165200 System and method for characterizing a signal path using a sub-chip sampler
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US Patent 7168014 Propagating an error through a network
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US Patent 7168019 Method and module for universal test of communication ports
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US Patent 7171599 Field programmable device
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US Patent 7174491 Digital system and method for testing analogue and mixed-signal circuits or systems
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US Patent 7178073 Test method and test apparatus for an electronic module
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US Patent 7181661 Method and system for broadcasting data to multiple tap controllers
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US Patent 7185248 Failure analysis system and failure analysis method of logic LSI
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US Patent 7185255 Test apparatus
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US Patent 7185265 Disk array system and its control method
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US Patent 7188281 Error correction coding apparatus and method
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US Patent 7188283 Communication signal testing with a programmable logic device
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US Patent 7188287 Semiconductor apparatus
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US Patent 7188294 High-efficiency error detection and/or correction code
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US Patent 7188299 Data-recording/reproduction apparatus and data-recording/reproduction method
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US Patent 7191379 Magnetic memory with error correction coding
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US Patent 7200786 Built-in self-analyzer for embedded memory
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US Patent 7200792 Interleaving apparatus and method for symbol mapping in an HSDPA mobile communication system
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US Patent 7203869 Test stream generating method and apparatus for supporting various standards and testing levels
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US Patent 7210078 Error bit method and circuitry for oscillation-based characterization
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US Patent 7210086 Long running test method for a circuit design analysis
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US Patent 7210088 Fault isolation through no-overhead link level CRC
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US Patent 7213186 Memory built-in self test circuit with full error mapping capability
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US Patent 7216268 Method and arrangement to estimate transmission channel characteristics
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US Patent 7216279 Testing with high speed pulse generator
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US Patent 7219272 Semiconductor integrated circuit with memory redundancy circuit
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US Patent 7219275 Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy
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US Patent 7219283 IC with TAP, STP and lock out controlled output buffer
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US Patent 7219285 Flash memory
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US Patent 7219287 Automated fault diagnosis in a programmable device
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US Patent 7222278 Programmable hysteresis for boundary-scan testing
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US Patent 7225376 Method and system for coding test pattern for scan design
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US Patent 7225391 Method and apparatus for parallel computation of linear block codes
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US Patent 7228480 Rate-1 coding for increasing timing information in recording data
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US Patent 7231574 Hardware mechanism for receiving frames from a link
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US Patent 7234087 External storage device and memory access control method thereof
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US Patent 7237155 Testing method for permanent electrical removal of an intergrated circuit output after packaging
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US Patent 7237156 Content addressable memory with error detection
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US Patent 7237158 Intelligent binning for electrically repairable semiconductor chips
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US Patent 7237162 Deterministic BIST architecture tolerant of uncertain scan chain outputs
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US Patent 7237167 Testing apparatus
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US Patent 7237172 Error detection and correction in a CAM
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US Patent 7237173 Recording and reproducing apparatus, signal decoding circuit, error correction method and iterative decoder
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US Patent 7240270 Method of transmitting signaling messages in a mobile telecommunications network
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US Patent 7243273 Memory testing device and method
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US Patent 7243275 Smart verify for multi-state memories
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US Patent 7243276 Method for performing a burn-in test
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US Patent 7246275 Method and apparatus for managing data integrity of backup and disaster recovery data
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US Patent 7246276 Error tolerant modular testing of services
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US Patent 7246282 Bypassing a device in a scan chain
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US Patent 7246287 Full scan solution for latched-based design
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US Patent 7246303 Error detection and recovery of data in striped channels
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US Patent 7254759 Methods and systems for semiconductor defect detection
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US Patent 7254760 Methods and apparatus for providing scan patterns to an electronic device
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US Patent 7257745 Array self repair using built-in self test techniques
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US Patent 7257746 System for protection link supervision
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US Patent 7260757 System and method for testing electronic devices on a microchip
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US Patent 7263639 Combinatorial at-speed scan testing
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US Patent 7266743 Combinatorial at-speed scan testing
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US Patent 7269767 Magnetic disk apparatus, preventive maintenance detection method and program therefor
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US Patent 7275197 Testing apparatus
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US Patent 7275198 Apparatus and method for transmitting/receiving error detection information in a communication system
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US Patent 7278078 Built-in self-test arrangement for integrated circuit memory devices
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US Patent 7281184 Test system and method for testing a circuit
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US Patent 7284168 Method and system for testing RAM redundant integrated circuits
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US Patent 7296196 Redundant column read in a memory array
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US Patent 7296197 Metadata-facilitated software testing
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US Patent 7299390 Apparatus and method for encrypting security sensitive data
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US Patent 7320102 Network processor having cyclic redundancy check implemented in hardware
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US Patent 7322005 LDPC (Low Density Parity Check) coded modulation symbol decoding using non-Gray code maps for improved performance
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US Patent 7328388 Built-in self-test arrangement for integrated circuit memory devices
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US Patent 7331005 Semiconductor circuit device and a system for testing a semiconductor apparatus
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US Patent 7353448 Methods, architectures, circuits and systems for transmission error determination
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US Patent 7356741 Modular test controller with BIST circuit for testing embedded DRAM circuits
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US Patent 7360130 Memory with integrated programmable controller
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US Patent 7363559 Detection of tap register characteristics
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US Patent 7636875 Low noise coding for digital data interface
Edits on 3 Dec, 2021
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Golden AI
edited on 3 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7636875 Low noise coding for digital data interface
Edits on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7363559 Detection of tap register characteristics
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7360130 Memory with integrated programmable controller
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7356741 Modular test controller with BIST circuit for testing embedded DRAM circuits
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7353448 Methods, architectures, circuits and systems for transmission error determination
Edits on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7331005 Semiconductor circuit device and a system for testing a semiconductor apparatus
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7328388 Built-in self-test arrangement for integrated circuit memory devices
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7320102 Network processor having cyclic redundancy check implemented in hardware
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7299390 Apparatus and method for encrypting security sensitive data
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7296197 Metadata-facilitated software testing
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7296196 Redundant column read in a memory array
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7284168 Method and system for testing RAM redundant integrated circuits
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7281184 Test system and method for testing a circuit
Golden AI profile picture
Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7278078 Built-in self-test arrangement for integrated circuit memory devices
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Golden AI
edited on 22 Nov, 2021
Golden AI profile picture
Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7275197 Testing apparatus
Golden AI profile picture
Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7269767 Magnetic disk apparatus, preventive maintenance detection method and program therefor
Golden AI profile picture
Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7266743 Combinatorial at-speed scan testing

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