US Patent 7219283 IC with TAP, STP and lock out controlled output buffer

Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. A first buffer has an input connected to a scan output lead, a control input, and an output connected to a serial data output lead. A first gate has an output connected to the control input of the first buffer, a scan output enable input connected to a scan circuitry control output lead, and a lock out signal input. A second buffer has an input connected to a test data output lead, an input connected to a buffer enable output lead, and an output connected to a serial data output lead. This structure provides for selecting data outputs between the TAP and internal scan test ports.