US Patent 7127482 Performance optimized approach for efficient downsampling operations
Patent 7127482 was granted and assigned to Intel on October, 2006 by the United States Patent and Trademark Office.
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Patent abstract
An algorithm and hardware structure is described for numerical operations on signals that is reconfigurable to operate in a downsampling or non-downsampling mode. According to one embodiment, a plurality of adders and multipliers are reconfigurable via a switching fabric to operate as a plurality of MAAC ( multiply-add-accumulator) kernels (described in detail below), when operating in a non-downsampling mode and a plurality of MAAC kernels and AMAAC (add-multiply-add-accumulator) kernals (described in detail below), when operating in a downsampling mode.
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US Patent 07127482 Performance optimized approach for efficient downsampling operations US Patent 7127482 Performance optimized approach for efficient downsampling operations
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Patent Number
0712748200
Patent Number
712748200
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Current Assignee
Patent Jurisdiction
Patent Number
071274820
Date of Patent
October 24, 2006
0Patent Application Number
099898570
Date Filed
November 19, 2001
0Official Website
Patent Primary Examiner
Edits on 23 Sep, 2022
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Current Assignee
Patent Jurisdiction
Patent Number
071274820
Date of Patent
October 24, 2006
0Patent Application Number
099898570
Date Filed
November 19, 2001
0Official Website
Patent Primary Examiner
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US Patent 07127482 Performance optimized approach for efficient downsampling operations
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07127482
Date of patent
October 24, 2006
Patent application number
09989857
Date Filed
November 19, 2001
Patent primary examiner
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