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US Patent 12124383 Systems and methods for cache optimization

Patent 12124383 was granted and assigned to Intel on October, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
0

Patent attributes

Patent Applicant
Intel
Intel
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Current Assignee
Intel
Intel
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
121243830
Patent Inventor Names
Pattabhiraman K0
Elmoustapha Ould-Ahmed-Vall0
Joydeep Ray0
Scott Janus0
Varghese George0
Brent Insko0
Altug Koker0
SungYe Kim0
...
Date of Patent
October 22, 2024
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Patent Application Number
178627390
Date Filed
July 12, 2022
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Patent Citations
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US Patent 7197605 Allocating cache lines
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US Patent 7327289 Data-modifying run length encoder to avoid data expansion
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US Patent 7346741 Memory latency of processors with configurable stride based pre-fetching technique
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US Patent 7373369 Advanced execution of extended floating-point add operations in a narrow dataflow
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US Patent 7483031 Method for synchronizing graphics processing units
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US Patent 7616206 Efficient multi-chip GPU
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US Patent 7620793 Mapping memory partitions to virtual memory pages
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US Patent 7873812 Method and system for efficient matrix multiplication in a SIMD processor architecture
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...
Patent Primary Examiner
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Shawn X Gu
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CPC Code
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G06F 12/123
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G06F 12/0875
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G06F 12/0891
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G06F 2212/302
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G06F 12/126
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G06T 1/60
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Patent abstract

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

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