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US Patent 12013808 Multi-tile architecture for graphics operations

Patent 12013808 was granted and assigned to Intel on June, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
0

Patent attributes

Patent Applicant
Intel
Intel
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Current Assignee
Intel
Intel
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120138080
Patent Inventor Names
Arthur Hunter0
Aravindh Anantaraman0
Joydeep Ray0
Saurabh Tangri0
Selvakumar Panneer0
Scott Janus0
Brent E. Insko0
Abhishek R. Appu0
...
Date of Patent
June 18, 2024
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Patent Application Number
174298730
Date Filed
March 14, 2020
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Patent Citations
‌
US Patent 7197605 Allocating cache lines
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US Patent 7327289 Data-modifying run length encoder to avoid data expansion
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US Patent 7346741 Memory latency of processors with configurable stride based pre-fetching technique
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US Patent 7373369 Advanced execution of extended floating-point add operations in a narrow dataflow
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US Patent 7483031 Method for synchronizing graphics processing units
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US Patent 7616206 Efficient multi-chip GPU
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US Patent 7620793 Mapping memory partitions to virtual memory pages
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US Patent 7873812 Method and system for efficient matrix multiplication in a SIMD processor architecture
0
...
Patent Primary Examiner
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Cheng Yuan Tseng
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CPC Code
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G06F 15/7839
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G06F 15/173
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G06F 12/0804
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G06F 12/0893
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Patent abstract

Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

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