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US Patent 12013808 Multi-tile architecture for graphics operations

Patent 12013808 was granted and assigned to Intel on June, 2024 by the United States Patent and Trademark Office.

Overview Structured Data Issues Contributors

Is a

Patent

Current Assignee

Intel

Date Filed

March 14, 2020

Date of Patent

June 18, 2024

Patent Applicant

Intel

Patent Application Number

17429873

Patent Citations

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US Patent 7197605 Allocating cache lines

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US Patent 7327289 Data-modifying run length encoder to avoid data expansion

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US Patent 7346741 Memory latency of processors with configurable stride based pre-fetching technique

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US Patent 7373369 Advanced execution of extended floating-point add operations in a narrow dataflow

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US Patent 7483031 Method for synchronizing graphics processing units

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US Patent 7616206 Efficient multi-chip GPU

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US Patent 7620793 Mapping memory partitions to virtual memory pages

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US Patent 7873812 Method and system for efficient matrix multiplication in a SIMD processor architecture

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US Patent 7913041 Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint

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US Patent 8253750 Digital media processor

•••

Patent Inventor Names

Arthur Hunter

Aravindh Anantaraman

Joydeep Ray

Saurabh Tangri

Selvakumar Panneer

Scott Janus

Brent E. Insko

Abhishek R. Appu

Ben Ashbaugh

Kamal Sinha

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Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

12013808

Patent Primary Examiner

CPC Code

Industry

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