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US Patent 12079155 Graphics processor operation scheduling for deterministic latency

Patent 12079155 was granted and assigned to Intel on September, 2024 by the United States Patent and Trademark Office.

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Patent attributes

Patent Applicant

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Current Assignee

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Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Patent Inventor Names

Varghese George1

Nilesh Jain1

Mike MacPherson1

Eric Samson1

Abhishek Appu1

Altug Koker1

Ravishankar Iyer1

Saurabh Tangri1

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Date of Patent

September 3, 2024

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Patent Application Number

174282161

Date Filed

March 14, 2020

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Patent Citations

US Patent 7197605 Allocating cache lines

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US Patent 7327289 Data-modifying run length encoder to avoid data expansion

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US Patent 7346741 Memory latency of processors with configurable stride based pre-fetching technique

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US Patent 7373369 Advanced execution of extended floating-point add operations in a narrow dataflow

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US Patent 7483031 Method for synchronizing graphics processing units

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US Patent 7616206 Efficient multi-chip GPU

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US Patent 7620793 Mapping memory partitions to virtual memory pages

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US Patent 7873812 Method and system for efficient matrix multiplication in a SIMD processor architecture

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Patent Primary Examiner

Jacinta M Crawford

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CPC Code

1

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Patent abstract

Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

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