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US Patent 12066975 Cache structure and utilization

Patent 12066975 was granted and assigned to Intel on August, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
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Patent attributes

Patent Applicant
Intel
Intel
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Current Assignee
Intel
Intel
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120669750
Patent Inventor Names
ElMoustapha Ould-Ahmed-Vall0
Altug Koker0
Varghese George0
Subramaniam Maiyuran0
Lakshminarayanan Striramassarma0
Aravindh Anantaraman0
Abhishek R. Appu0
Valentin Andrei0
...
Date of Patent
August 20, 2024
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Patent Application Number
174292910
Date Filed
March 14, 2020
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Patent Citations
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US Patent 8488055 Flash synchronization using image sensor interface timing signal
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US Patent 8645634 Zero-copy data sharing by cooperating asymmetric coprocessors
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US Patent 8669990 Sharing resources between a CPU and GPU
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US Patent 8847965 Methods, systems, and computer readable media for fast geometric sound propagation using visibility computations
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US Patent 8990505 Cache memory bank selection
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US Patent 9304835 Optimized system for analytics (graphs and sparse matrices) operations
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US Patent 9317251 Efficient correction of normalizer shift amount errors in fused multiply add operations
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US Patent 9461667 Rounding injection scheme for floating-point to integer conversion
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Patent Primary Examiner
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Shawn X Gu
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CPC Code
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G06T 15/06
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G06F 15/7839
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G06F 7/5443
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G06F 7/575
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G06F 7/588
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G06F 9/3001
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G06F 9/30014
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G06F 9/30036
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Patent abstract

Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

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