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Naum Levin

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Edits on 14 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 14 Dec, 2021
Edits made to:
Infobox (-42 properties)
Infobox
Patent primary examiner of
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US Patent 11180048 Transport-based exchange of electrical charge and services
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US Patent 11182530 Automatic routing system workflow
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US Patent 11182533 Standard cells and variations thereof within a standard cell library
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US Patent 11185203 Robot cleaner, charging device and charging system
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US Patent 11188698 Method for integrated optimization of ternary FPRM circuit
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US Patent 7913217 Visualizing hardware cost in high level modeling systems
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US Patent 7926007 Writing apparatus, writing data conversion method, and computer-readable recording medium storing program using Huffman tree for converting writing data in lithographic process
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US Patent 7926016 Timing driven logic block configuration
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US Patent 7930670 Using selectable in-line inverters to reduce the number of inverters in a semiconductor design
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US Patent 7930673 Method for automatic clock gating to save power
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US Patent 7934174 Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout
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US Patent 7937682 Method and apparatus for automatic orientation optimization
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US Patent 7941773 Simulation system to verify multicycle path based on circuit operational specification and circuit design specification
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US Patent 7945884 Backplane routing arrangement with decreased crosstalk
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US Patent 7945887 Modeling spatial correlations
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US Patent 7949990 Parallel electronic design automation: shared simultaneous editing
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US Patent 7954071 Assist feature placement based on a focus-sensitive cost-covariance field
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US Patent 7954072 Model import for electronic design automation
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US Patent 7958476 Method for multi-cycle path and false path clock gating
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US Patent 7958480 Placement of I/O blocks within I/O banks using an integer linear programming formulation
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US Patent 7962881 Via structure to improve routing of wires within an integrated circuit
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US Patent 7962883 Developing semiconductor circuit design with conditional flipflops to save power consumption
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US Patent 7966580 Process-model generation method, computer program product, and pattern correction method
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US Patent 7966581 Generic non-volatile service layer
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US Patent 7966585 Selective shielding for multiple exposure masks
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US Patent 7971158 Spacer fill structure, method and design structure for reducing device variation
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US Patent 7971169 System and method for reducing the generation of inconsequential violations resulting from timing analyses
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US Patent 7971174 Congestion aware pin optimizer
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US Patent 7975245 Computer-implemented methods for determining if actual defects are potentially systematic defects or potentially random defects
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US Patent 7979836 Split-gate DRAM with MuGFET, design structure, and method of manufacture
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US Patent 7984396 Apparatus and method for dummy pattern arrangement
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US Patent 7984415 Merging of equivalent logic blocks in a circuit design
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US Patent 7987440 Method and system for efficient validation of clock skews during hierarchical static timing analysis
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US Patent 7987441 Method and architecture for power gate switch placement
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US Patent 7992120 Congestion estimation for programmable logic devices
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US Patent 7992121 System and method for I/O synthesis and for assigning I/O to programmable devices
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US Patent 8001494 Table-based DFM for accurate post-layout analysis
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US Patent 8001498 Method and apparatus for memory abstraction and verification using same
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US Patent 8001517 Layout design method of semiconductor integrated circuit cell to adjust distances inside cell between diffusion layers and borders of cell
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US Patent 8006218 Power mesh arrangement method utilized in an integrated circuit having multiple power domains
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US Patent 8010930 Extracting consistent compact model parameters for related devices
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US Patent 8010931 Tool for a configurable integrated circuit that uses determination of dynamic power consumption
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8010930 Extracting consistent compact model parameters for related devices
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Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8001498 Method and apparatus for memory abstraction and verification using same
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8001494 Table-based DFM for accurate post-layout analysis
Edits on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7992121 System and method for I/O synthesis and for assigning I/O to programmable devices
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7992120 Congestion estimation for programmable logic devices
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7987441 Method and architecture for power gate switch placement
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7984415 Merging of equivalent logic blocks in a circuit design
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7984396 Apparatus and method for dummy pattern arrangement
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7979836 Split-gate DRAM with MuGFET, design structure, and method of manufacture
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7971174 Congestion aware pin optimizer
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7971158 Spacer fill structure, method and design structure for reducing device variation
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7966580 Process-model generation method, computer program product, and pattern correction method
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7966581 Generic non-volatile service layer

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