MEARS Technologies

US Patent 7303948 Semiconductor device including MOSFET having band-engineered superlattice

US Patent 7432524 Integrated circuit comprising an active optical device having an energy band engineered superlattice

US Patent 7433729 Infrared biometric finger sensor including infrared antennas and associated methods

US Patent 7435988 Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel

US Patent 7436026 Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions

US Patent 7446002 Method for making a semiconductor device comprising a superlattice dielectric interface layer

US Patent 7446334 Electronic device comprising active optical devices with an energy band engineered superlattice

US Patent 7491587 Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer

US Patent 7514328 Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween

US Patent 7517702 Method for making an electronic device including a poled superlattice having a net electrical dipole moment

US Patent 7531828 Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions

US Patent 7531829 Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance

US Patent 7531850 Semiconductor device including a memory cell with a negative differential resistance (NDR) device

US Patent 7535041 Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance

US Patent 7586116 Semiconductor device having a semiconductor-on-insulator configuration and a superlattice

US Patent 7586165 Microelectromechanical systems (MEMS) device including a superlattice

US Patent 7598515 Semiconductor device including a strained superlattice and overlying stress layer and related methods

US Patent 7612366 Semiconductor device including a strained superlattice layer above a stress layer

US Patent 7625767 Methods of making spintronic devices with constrained spintronic dopant

US Patent 7659539 Semiconductor device including a floating gate memory cell with a superlattice channel

US Patent 7700447 Method for making a semiconductor device comprising a lattice matching layer

US Patent 7718996 Semiconductor device comprising a lattice matching layer

US Patent 7781827 Semiconductor device with a vertical MOSFET including a superlattice and related methods

US Patent 7812339 Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures

US Patent 7863066 Method for making a multiple-wavelength opto-electronic device including a superlattice

US Patent 7880161 Multiple-wavelength opto-electronic device including a superlattice

US Patent 7928425 Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods