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US Patent 7718996 Semiconductor device comprising a lattice matching layer

Patent 7718996 was granted and assigned to MEARS Technologies on May, 2010 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Current Assignee
MEARS Technologies
MEARS Technologies
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
77189960
Patent Inventor Names
Robert J. Mears0
Ilija Dukovski0
Jean Augustin Chan Sow Fook Yiptong0
Marek Hytha0
Robert John Stephenson0
Samed Halilov0
Xiangyang Huang0
Date of Patent
May 18, 2010
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Patent Application Number
116770980
Date Filed
February 21, 2007
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Patent Citations Received
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US Patent 11978771 Gate-all-around (GAA) device including a superlattice
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US Patent 12014923 Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice
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US Patent 11664427 Vertical semiconductor device with enhanced contact structure and associated methods
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US Patent 11664459 Method for making an inverted T channel field effect transistor (ITFET) including a superlattice
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US Patent 11682712 Method for making semiconductor device including superlattice with O18 enriched monolayers
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US Patent 12020926 Radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice
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US Patent 11837634 Semiconductor device including superlattice with oxygen and carbon monolayers
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Patent Primary Examiner
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Wai-Sing Louie
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Patent abstract

A semiconductor device may include a first monocrystalline layer comprising a first material having a first lattice constant. A second monocrystalline layer may include a second material having a second lattice constant different than the first lattice constant. The device may also include a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. The superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.

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