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US Patent 7718996 Semiconductor device comprising a lattice matching layer

Patent 7718996 was granted and assigned to MEARS Technologies on May, 2010 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Current Assignee
MEARS Technologies
MEARS Technologies
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Date Filed
February 21, 2007
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Date of Patent
May 18, 2010
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Patent Application Number
11677098
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Patent Citations Received
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US Patent 11978771 Gate-all-around (GAA) device including a superlattice
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US Patent 12014923 Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice
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US Patent 11664427 Vertical semiconductor device with enhanced contact structure and associated methods
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US Patent 11664459 Method for making an inverted T channel field effect transistor (ITFET) including a superlattice
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US Patent 11682712 Method for making semiconductor device including superlattice with O18 enriched monolayers
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US Patent 12020926 Radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice
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US Patent 11837634 Semiconductor device including superlattice with oxygen and carbon monolayers
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US Patent 12119380 Method for making semiconductor device including superlattice with oxygen and carbon monolayers
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US Patent 11869968 Semiconductor device including a superlattice and an asymmetric channel and related methods
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US Patent 11923418 Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
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•••
Patent Inventor Names
Robert J. Mears
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Ilija Dukovski
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Jean Augustin Chan Sow Fook Yiptong
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Marek Hytha
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Robert John Stephenson
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Samed Halilov
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Xiangyang Huang
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
7718996
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Patent Primary Examiner
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Wai-Sing Louie
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