US Patent 9679650 3D NAND memory Z-decoder

Apparatus and methods are disclosed, including an apparatus having first and second units of vertically arranged strings of memory cells, each unit including multiple tiers of a semiconductor material, each tier including an access line of at least one memory cell and a channel of a decoder transistor, wherein the channel of the decoder transistor of each of the multiple tiers of the first unit of memory cells is coupled to the channel of the decoder transistor of a corresponding tier of the second unit of memory cells. Methods of forming such apparatus are disclosed, as well as methods of operation, and other embodiments.