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US Patent 8841765 Multi-chip module with stacked face-down connected dies

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US Patent RE49987 Multiple plated via arrays of different wire heights on a same substrate
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edited on 22 May, 2024
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US Patent 11990382 Fine pitch BVA using reconstituted wafer with area array accessible for testing
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edited on 14 Mar, 2024
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US Patent 11929337 3D-interconnect
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US Patent 11854785 Package structure for heat dissipation
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edited on 27 Sep, 2023
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Patent Inventor Names
Belgacem Haba0
Ilyas Mohammed0
Piyush Savalia0
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edited on 16 Jul, 2023
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US Patent 08841765 Multi-chip module with stacked face-down connected dies US Patent 8841765 Multi-chip module with stacked face-down connected dies

Infobox
Patent Number
088417650
Patent Number
88417650
Edits on 25 May, 2023
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edited on 25 May, 2023
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=088417650
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edited on 5 Apr, 2023
Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
088417650
Date of Patent
September 23, 2014
0
Patent Application Number
130923760
Date Filed
April 22, 2011
0
Official Website
https://pdfpiw.uspto.gov/.piw?Docid=088417650
Patent Primary Examiner
‌
S. V. Clark
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Edits on 15 Jun, 2022
"Entity importer update"
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edited on 15 Jun, 2022
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=08841765
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created this topic on 26 Dec, 2021
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 US Patent 08841765 Multi-chip module with stacked face-down connected dies

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
08841765
Date of patent
September 23, 2014
Patent application number
13092376
Date Filed
April 22, 2011
Patent primary examiner
‌
S. V. Clark

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